Rep:Re: [f-cpu] New suggestion about call convention

["Nicolas Boulay" <nicolas.boulay@ifrance.com>]

-----Message d'origine-----
De: Yann Guidon <whygee@f-cpu.org>
A: f-cpu@seul.org
Date: 07/11/02
Objet: Re: [f-cpu] New suggestion about call convention



Michael Riepe wrote:

>On Wed, Nov 06, 2002 at 11:43:11AM +0100, whygee@club-internet.fr
wrote:
>[...]
>  
>
>>i get the picture.
>>
>>However, due to the nature of some 2W instructions,
>>the "capo" MUST be done with pairs of registers, on a
>>"granularity" of 2. That is : you can't do half-tone
>>pitch shifting.
>>    
>>
>
>Right.
>
i hope that this restriction will not frustrate too much anybdy....

>>Still there is a problem with loadm and storem.
>>    
>>
>
>If loadm/storem aren't available, we can still use explicit
>load/store instructions.
>
i think that the "explicit" instructions are going to be used for a
while
because the LSU and Xbar are not designed to handle 4 words at a time.
They can do 2 words but LSU has only 1 read and 1 write port (+
address).

>>>> I don't see any problem for that.

Otherwise, handling more register at once will explode the bypass 
logic's size.

>>>I have soon write some graph on it but it became old and i forgot
about it.

i hope that nicO understands the problem. So "storem" and "loadm" seem
to be very limited (2 words) and i am not even sure that it is still 
"safe" in FC0.

>>> 2 words is not so interesting, 8 or 4 is much better (8 imply very
very large datapath).

For example, alignment is a big problem : what to do when the 2 words
are not aligned on a LSU line boundary, or across pages ?....

>>>For something simple it must be memory aligned to enable the load of
a complete cache line. Otherwise, the data path will be full of muxes.
So there is no exception problem. If you enable that feature, it's
always the same : check the exception the earlier.

if strict alignment is required, then the stack will bloat (filled with
empty slots). If it is allowed, then a lot of HW problems are to be
solved.

>>> ? Why ?
For better data handling, we must consider 2 cases SIMD or not.
Otherwise, if all mload/mstore are SIMD, using it for scalar operation
will be a mess.

If one wants more bandwidth, then a PFQ-based architecture is required,
but it requires a complete redesign of everything.

>>>a WHAT ?
nicO

YG


*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/

__________________________________________________
Modem offert : 150,92 euros remboursés sur le Pack eXtense de Wanadoo ! 
Haut débit à partir de 30 euros/mois : http://www.ifrance.com/_reloc/w


__________________________________________________
Modem offert : 150,92 euros remboursés sur le Pack eXtense de Wanadoo ! 
Haut débit à partir de 30 euros/mois : http://www.ifrance.com/_reloc/w

*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/