Re: [f-cpu] optional SRB

[Antoine <antoine@rezo.net>]

For IRQ/trap handlers you probably also need :

- a SR_PC which automatically holds the PC value just before the
context switch

- a set of temporary SRs with no other purpose than holding
temporary values (let's say SR_TMP0 ... SR_TMP3). This because
you need to save some registers before even the register save
pointer is set up (at the very least you need to save the registe
that will contain the register save pointer :-))

- an instruction which takes SR_PC and loads it into the PC.
The instruction that returns from an IRQ/trap handler cannot
use a general-purpose register, because the interrupted
thread (or whatever you call it) needs to have all its registers
untouched. This instruction could be called "reti" (return from
interrupt).

- an EI instruction to re-enable interrupts. Indeed, when a IRQ/trap
is launched, interruptions should be automatically disabled by the
CPU, because the very beginning of the handler will not be reentrant ;
then you will re-enable them after the non-reentrant part is finished
(which probably means when all registers are successfully saved).
The DI instruction is optional.

To my opinion this should be sufficient. The rest can be handled
in software, for example by having a software-managed stack dedicated
to context-switches.

(please note : I am no systems programmer ;-))


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