Re: [f-cpu] Smooth Register backup issues...

[nico@seul.org]

>>
>> Or ARM. That's called swadow register. The problem with SRB is :
>> - how do you handle nested interrupt ?
>> - how do you "allocate" a new CMB ?
>> - If saving is automatique even on very light it handler you must save
>> all
>> of the register.
>
>   But would a "shadow stack" be a bad idea? Like, instead of
> one shadow-register, there would be, let's say, 1000-level deep stack??
> OK, it takes up some mount of silicon or some quantity of gates in the
> FPGA case, but it should work somehow... And after the stack get's filled,
> it's being automatically saved(and later retreived) to(from) some,
> specially reserved region of the system's memory. All the housekeeping
> would be the job for the memory management unit.
> After all, the newest CPU's do have onboard
> caches with sizes reaching atleast to 1MB. In the VHDL-code,
> the ctack size can be stored in a variable, so, if anybody wants, he/she
> set's it to 1, 10, 100, or what ever her/his hardware can afford.
>   I'm a newby chip design's point of view, so, I hope You don't mind my
> huge technical mistakes and I hope that my mistakes are getting
> corrected.

That's a udge silicium area, with some system to prevent overflow and so
one. That's complicated for almost no benefit at all. OS as linux didn't
use such hardware OS support because it use the less common denominator
between cpus.

nicO

>
> Regards,
>   Martin Vahi
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