[f-cpu] Re: La MMU du f-cpu

[Pierre Tardy <tardyp@free.fr>]

On Mon, 17 Nov 2003 16:02:37 +0100
Yann Guidon <whygee@f-cpu.org> wrote:

> je ne savais pas que le code de Michael était si avancé mais il y a 
> plein de choses à vérifier !
> 
> surtout et en premier lieu que tout marche au poil en 64 bits, 128 bits, > 256 bits etc.
> car c'est pas tout de coder, il faut /bien/ coder :-/
> 
> et puis la LSU est assez sophistiquée.
> si vous voulez un truc réaliste au niveau du trafic mémoire
> et modélisation de latence, il faut passer par là.


Well in fact we are talking about 2 different levels of simulation.
see http://www.ee.princeton.edu/~wqin/armsim.htm
SimIt is the name of a series of free instruction-set-simulators and micro-architecture simulators

The first level (on what I'm working) is the instruction set simulator and is not cycle accurate or "memory access acurate". In this one, the complicated LSU and Fetcher are very simplified, the simulation is very fast.

Then there is the micro-architecture simulator, LSU, Fetcher and cache are here very closed to the reality. This is far more complicated and I dont know if 3 month is enough.. 

I think the first step for us, will be to implement an ISS (in the meaning of SimIt) based on Michael's work, to connect it with some RAM and some ROM containing some testing binary. I dont know today the time that it will take us, but I'm pretty sure that we will achieve this step before february.

The next steps may be to implement the Fetcher then the LSU then the caches. At this time, I 've no idea  how long it can take us.

greets,
-- 
Pierre
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