Re: [f-cpu] Re: La MMU du f-cpu

[nico@seul.org]

> Hi Pierre et al,
>
> Pierre Tardy wrote:
>
>> I 'm talking in this thread about my school project to make an ISS
>> based on your emulator. I said that your code is pretty advanced (not
>> quoted) and he say me that I have to verify if it will work
>> simulating a 64, 128 or 256 bits processor. Then he ask me to produce
>> good code. :)
>
> IC. To answer that question: The emulator is prepared to handle wider
> operands. I already compiled it for a 4096-bit CPU :) Special registers
> are still 64-bit wide but that may change in the future.

Juste to be sure of what we speak about. A 256 bits f-cpu use 4x64, 8x 32,
16x16, 32*8 bits words. It's not a question of using 256, 8x32,16x16,32x8
bits registers ? Thats simd instruction, otherwise it always use 64 32 16
8 bits in scalar.

Since a long time i sugest to think in terme of 256 bit F-cpu, it's easier
to make cut down rather than inflating the design. For 64 bits flotting
point code, vector of 4 double are the optmimum for the floating point
spec benchmark according to a studies. Wider register decrease the speed
because of too much data dependancies.

Beside that thinking in term of 64 bits are to narrow, we miss all pitfall
of having too few inter-schunk data manipulation. At least some "move"
schould be introduice to enable easier vectorised code. To complicate
things, those "move" should be mostly O(1) and not O(n) with n the number
of 64 bits schunk.

nicO

>
>
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