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Re: [f-cpu] 'make it work' or 'make it fast' ?



Yann Guidon a écrit :
> 
> hi,
> 
> since i am studying at ASIME, i have learnt some
> basics about using the "homemade" Alliance toolchain.
> 
> I can make several reproaches about it : it is "a bit heavy",
> does not comply to the VHDL standard coding practices,
> but i begin to realize that it is not really a VHDL tool :
> in fact it is more a synthesis tool. It has the advantage
> that you can design masks relatively easily and quickly.
> 
> However, from what i can see, the use of their precharacterised
> library is not the best way to make a "fast" CPU, if you consider
> that if you want to make custom ASIC, you want to get all
> the power you expect from this. On one side, you reduce the
> pressure on the post-synthesis tools (timing/parasitics/etc)
> but on the other side, you can get almost the same speed
> (and probably more) with the latest FPGAs (who support the
> most recent synthesis algorithms with fully VHDL compliant sources).
> This is because, from what i have seen, their strategy is
> underefficient, particularly with P&R and post-layout compression
> (there's often wasted surface). This is maybe my PCB designer's eyes
> that tell me that.
> 
> But i can't deny that having a working F-CPU sooner is attracting.
> So there's the old dilemma : do we sacrifice source portability,
> clock speed and high-level synthesis ? Or do we accept to go the
> route of early prototypes ?

You need to use the library from a foundry. Does Alliance accept
synopsys library file ?

Could you create SDF file to simulate it with timing (after synthesys)?

> It would be cool if Alliance accepted VHDL'93 sources, or even
> FOR .. GENERATE loops !!!
> 

Alliance doesn't support "process", too...

On of your teacher M Jacome made a thesis to write a wrapper from
"clean" synposys VHDL to dirty alliance VHDL.

nicO

> WHYGEE
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