Re: [f-cpu] X-Bar replacement and PoC of massiv-parallel-computing,hints?

[Andreas Romeyke <art1@it-netservice.de>]

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Hello,

> I'd rather use an array of ALUs, with separate row and column buses
> and dedicated links to their neighbours (much like the cells in an
> FPGA).  Or maybe a ring.

No, the advantage comes with a 2-wired differential bus. A ring or an 
array complicates the bus-interface and  increases the HF-function.

> The second point is: why do you want to use S/P and P/S converters?

Why not?

S/P and vice versa is easy to build. Today, I have some discussions, a
2-wired bus with +high, low and -high levels are very fast, because we
have signals like this:

a: +high low -high +high -high low
b: -high low +high -high +high low

so the sum of levels on a and b are always zero. Also with 3 logic levels
we have the the chance to reduce/compress bitrate with 4b3t-code like in
ISDN-systems (remember: 4 clocks in binary code means 16 combinations, 3
clocks in ternary code means 27 combinations, there also some ternärcodes
free to use as sync) 

> > Can we use the concept of 2-wired bus with serial de/encoder on every unit
> > in f-cpu instead x-bar? 
> 
> That's too slow.  Remember that the bus must be much faster than the
> EUs, since we'll only be able to issue one instruction every 64 bus
> clock ticks (if there are seperate buses for each operand).

No, it is not, if we have a EUs-clock of 1ms, we have on serial bus a
clock of:

size_of_register
- ---------------- * 3  => bits/1ms + overhead_of_headers
4 * (sum of EUs)


But, one serial bus with 2 lines in above described technology is easier
in handling than a parallel bus with 64 or more lines with a line clock
less than serial.

Remember, a parallel bus is a capacity and frequency-sensitive and costs
many of logic (see X-bar or Shifting-unit).

BTW, my english is quite rare, but I hope you understand me...

Bye Andreas
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