Re: [f-cpu] freeze signal

[nicO <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
> 
> On Mon, Oct 08, 2001 at 01:42:54PM +0000, nicolas.boulay@ifrance.com wrote:
> > Is it possible to add a signal to the entities to
> > completly freeze its output. It's different from
> > enable. The freeze signal must stop the pipeline or
> > at least the output port of the unit, no new data
> > should get out in the result port.
> 
> Currently, the EUs contain no input or output registers at all; they're
> supposed to be added at the next higher level.
> 

So how do you make the pipeline, i miss some thing !

> > We absolutely need this kind of stuff to handel unit
> > with a latency more than 1 (to manage the fact to
> > have 2 data could be ready in the same time)
> 
> The scheduler has to take care of that.  It must delay the instruction
> if there is no free "transport slot".

Yep, you must insert a delay so you must at least stop the current flow
or you could try to predict the cas e (but i wait an algorythme for
that). In the first case, i need a signal to stop the pipeline (or stop
to produice output) to insert an empty slot.

nicO

> 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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