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Re: [f-cpu] registers
Michael,
Michael Riepe wrote:
>>I guess you are planning to fit an iteration in one cycle so we maintain
>>1bit/iteration throughput. The only way that I see to acheive this, for
>>larger chuncks than 8 bits, is using CSAs for partial reminder(PR)
>>computation and archiving it in redundant form.
>>
>>On the other hand, this architecture probably would work pretty good for
>>the SIMD datapath.
>
>
> That's right.
>
Glad to see that we are on the same page.
>
>>I think you said that you a block diagram of the Divider you're
>>designing. I would be glad to see it.
>
>
> That was somebody else. But the picture is pretty simple: The operands
> are normalized and fed into the SRT core. <n> cycles later, the core
> delivers <n>-bit quotients and remainders, both in redundant form.
> If the remainders have the wrong sign, the result is corrected. Finally,
> the result is denormalized and converted back to normal binary encoding.
>
When you normalize operands, in which range do you keep the divisor?
[-1/2,1/2]?
How about "Quotient Selection" mecanism?
Just compare PR to 0 and -1/2?
How many bits do you use from the redundant representation to decide?
Do you plan to add, let's say, the 4 MSB of the sum and carry
representations of the PR and then compare it to -1/2 and 0? or use a
256x2 table/PLA to generate quotient digit?
The PLA solution looks more efficient timing wise vs "small adder + one
gate stage for decoding". Playing some tricks with the encoding would
reduce its size and so keep its "access" time reasonable in order to
acheive: Quotient Selection + D/Not(D) Mux Slection + CSA stages for PR
computation + miscellaneous logic < 6 gates.
I am just curious how do you manage to keep the critical path for an
iteration under 6G/10T. Honnestly, I am having trouble doing it. :)
>
>>If you could also incorporate the code you have in the repository on
>>seul.org so I can be really up to date.
>
>
> It's not finished yet, and I never release code that doesn't work.
>
I would be glad to help as much as I can.
>
>>By the way, I have a general question about SIMD registers. I have read
>>in the manual that any 64 bit general purpose register would have a flag
>>indicating if it is a SIMD register or not. how about the SIMD mode?
>
>
> No, that's wrong. Instructions have a SIMD flag, but not registers.
>
thanks to Christophe and Yann, I understand better the situation.
Dali
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