Re: [f-cpu] Re: Testing Hardware

[Kim Enkovaara <kenkovaa@cc.hut.fi>]

On Fri, 7 Sep 2001, Michael Riepe wrote:

> > VirtexII 6000-6 bf957.
> > 
> > Speed: ~72MHz
> 
> Is that good or bad for that particular FPGA?

I think that is quite good. It's the fastest FPGA available, but 64-bit
multiplier is quite a big block. Also VII/6000 is the biggest FPGA chip
that is available currently (for some customers as samples). I can on
monday test what Synplify does if I just say A*B for 64 bit vectors
and give 6 clocks time for that and enable pipelining :) Synplify should
make better multiplier than Xilinx coregen at least. I just have to figure
out a way where Synplify won't use the internal multipliers of VirtexII.

> > Utilization: 29%
> 
> How can it become *smaller* when pipelining is turned on?
> Or is that caused by the missing speed constraints?

I think one reason is that the combinatorial part is much smaller
(between flipflops) and that is easier to fit to FPGA structures. In
FPGA one logic block is limited to 4 inputs. The schematic view had
something like 400 sheets. I didn't have time do look what the
synthesis really produced. 

=============================================================================
Mr. Kim Enkovaara   | kim.enkovaara@iki.fi | Microelectronic Riemannian
Vasamatie 1 C 16    | IRC: embo            | curved-space fault in
02630 Espoo         |                      | write-only file system

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