Re: [f-cpu] making things work

[Michael Riepe <michael@stud.uni-hannover.de>]

Hi *,

On Mon, Sep 10, 2001 at 10:45:16PM +0200, whygee@club-internet.fr wrote:
> 
> my local work directory has reached new size heights.
> The (future) inclusion of Michael's assembler won't help :-P

You should see mine ;)

> Michael Riepe <michael@stud.uni-hannover.de> :
> >On Sun, Sep 09, 2001 at 08:52:51PM +0200, whygee@club-internet.fr wrote:
> >[...]
> >> >> Btw, i will have to modify your ASU (at least)
> >> >> because things have evolved quite a bit in the last months...
> >> >What exactly?  Please send patches if possible.
> >> there are only a few changes necessary.
> >> max_chunck_size for example.
> >
> >MAX_CHUNK_SIZE must currently be 64 -- the adder doesn't handle 32-bit
> >(and probably never will -- it may be easier to write a separate 32-bit
> >version, and let the EU_IMU wrapper entity include the appropriate one).
> 
> Yes but it seems that the symbolic names have been moved
> or renamed or something like that. I'll have to fix that...

It's still called MAX_CHUNK_SIZE in eu_asu/asu.vhdl.

> >> Btw i would like to 'split' the ASU into two parts,
> >> so that the clocking can be done at a higher level.
> >
> >The stages are already separate processes (that is, they're easy to
> >separate), and the pipeline register is concentrated at the end of the
> >first stage.
> 
> would it be possible, then, to split the ASU in two files ?
> i'll try when i can...

Of course it's possible.  But is it also reasonable?

> >> Or if it is possible to define (once again) a 'generic'
> >> pipeline latch ... so as few changes as possible are necessary
> >> if the latches have to change.
> >
> >That would mean that we have to use a register component again (I'd prefer
> >a concurrent procedure, because it would make the code more readable, but
> >some synthesis tools don't grok edge expressions in a procedure. *argh*).
> 
> I have the intention of doing the 'clocking' in the top level
> VHDL file.

What's the reason for that?

You may have noticed that both ASU and IMU have an `enable' port now;
Nicolas convinced me to add that.  The signal is supposed to be raised
when an instruction is issued, and propagates through the pipeline,
depending on the current mode of operation (that is, the later stages are
disabled when you do an 8-bit multiplication, for example).  That's hard
to do at the outer levels.

> >[...]
> >> btw concerning your asm, it complains about some missing ELF
> >> libraries :-(
> >
> >Didn't I mention that it won't compile? ;)   Before you try again,
> >install the latest libelf pre-release from my homepage; the URL is
> >http://www.stud.uni-hannover.de/~michael/software/libelf-0.7.1-pre6.tar.gz
> >But please do not publish this ANYWHERE!
> 
> i'm downloading the tgz.
> will you put your asm on the GAOS CVS later/one day ?

Once the sources are stable.  I will have to move files and directories
around a lot when I add the other tools to the package, and it's better
not to do that in CVS ;)

> Concerning the clock : using the 'ugly' architecture
> is dangerous. I discovered that i had messed up the NCO loop.

Shit happens ;)

In general, ugly code tends to produce ugly errors.
Did you see my simple NCO entity, btw?

> I have moved the generic_adder stuff to a 'common' directory.
> Reading it was very interesting and i discovered new VHDL
> tricks... but i didn't know (reading the testbench) that
> one could instanciate a procedure... Maybe i didn't understand
> well because when i wanted to code a similar stuff,
> the compilers complained. I'm still a newbie...

You can use a procedure as a concurrent statement when all of its
outputs are declared as signals.  If they're variables, the procedure
will work only as a sequential statement (that is, inside a process).
That's why there are the S_* procedures in the Generic_Adder package.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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