Re: [f-cpu] new snapshot

[Michael Riepe <michael@stud.uni-hannover.de>]

Hi *,

> Btw, i think that Michael mentioned a correction
> to the clock's NCO but i have seen no code or URL yet.

No, that was a misunderstanding.  I wrote a small NCO entity a while
ago but I wasn't sure whether I sent it to the list.  Obviously, I
didn't.  Here it comes...

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
-- nco.vhdl -- Numerically Controlled Oscillator
-- Copyright (C) 2001 Michael Riepe <michael@stud.uni-hannover.de>
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

-- $Id$

library IEEE;
use IEEE.std_logic_1164.all;
use work.Generic_Adder.all;

entity NCO is
	generic (
		WIDTH : natural := 4
	);
	port (
		-- clock frequency value
		Freq : in std_ulogic_vector(WIDTH-1 downto 0);
		-- load new clock frequency value
		Load : in std_ulogic;
		-- input clock
		Clk_In : in std_ulogic;
		-- stop NCO
		Hold : in std_ulogic;
		-- reset NCO
		Rst : in std_ulogic;
	--
		-- output clock
		Clk_Out : out std_ulogic
	);
end NCO;

architecture Behave_1 of NCO is
begin
	process (Freq, Load, Clk_in, Hold, Rst)
		variable counter, delta, y, c : std_ulogic_vector(WIDTH-1 downto 0);
		variable g, p, o : std_ulogic;
	begin
		if to_X01(Rst) = '1' then
			counter := (others => '0');
			delta := (others => '0');	-- soft start
			o := '0';
		elsif rising_edge(Clk_in) then
			if to_X01(Hold) /= '1' then
				CIAdd(counter, delta, y, c, g, p);
				counter := y xor c;
				if to_X01(g or p) = '1' then
					if to_X01(Load) = '1' then
						delta := Freq;
					end if;
					o := not o;
				end if;
			end if;
		end if;
		Clk_Out <= o;
	end process;
end Behave_1;

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