Re: [f-cpu] License issues GPL/LGPL and Juergen Goeritz' SoC

[nicO <nicolas.boulay@ifrance.com>]

Michael Riepe a écrit :
<...>
> > Otherwise, stick with LEON : having a lot of CPU power is not
> > interesting if you're 'memory-bound' whatever you do. Cache miss
> > rates and refill speed kills all CPU. So at least with LEON you
> > are not too much memory bound.
> >
> > My current view for a "decent" F-CPU chip is :
> > - SDRAM (DDR/whatever) direct interface with the core
> > - onchip L1 cache (low latency)
> > - onchip L2 with very wide words, such as suggested by nicO, ie with DRAM,
> >   so we can do very wide SIMD computations
> 
No, don't mix things. I think as leon. It's like a canonical cpu. Leon
are core+L1 cache then it used AMBA bus to connect memory controleur and
so on (UART...). You could what ever speed you by enlarge the bus.
Wichbone coulb be extend 256 bits for internal use.

So fcpu core will only be the core+cache(unified or separate). All
others things could be include in a "plateforme". I think about
controler, L2 cache but we can add interrupt controler and so on (IO
quick link ). Imagine a router, it don't need SDRAM. 

So to the outside world, we could have coprocessor interface (as leon ?)
+ bus interface (wishbone). That's could clairly defined API.

nicO

> > - some kind of relatively fast interface to the outside, possibly
> >   with rather wide words (64-bit or 128-bit at a time) if it is on-chip.
> 
> I like the FSB of the MP-Athlon... it's a fast point-to-point link
> (200/266 MHz, using DDR), 64-bit wide with separate, unidirectional
> control buses.  It somehow reminds me of the F-BUS ;)
> 
> --
>  Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
>  "All I wanna do is have a little fun before I die"
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