[f-cpu] genereic_adder patch

[Yann Guidon <whygee@f-cpu.org>]

hello,

Here is a tiny modification to Michael's generic adder package.
The newest version of simili doesn't like the way the agregate
was used, but it is not too difficult to work around it.

Concerning the different way to initialize the signals
with random, i search an elegant and cheap way to bypass
the limitation imposed by Vanilla.

As written before, Simili accepts this :
  Signal s : std_ulogic_vector(N downto M) := random(s);
But i am forced to write this if i want to use Vanilla :
  Subtype t is std_ulogic_vector(N downto M);
  Signal  s is t := random(t'(others=>'0'));

I believe that it is due to the difference of parsing
engine : Vanilla uses yacc and the symbol table management
is maybe not perfect inside a single definition.

However, i don't want to define a subtype for every signal.
Is there a solution ?

WHYGEE
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generic_adder.vhdl.diff