Re: [f-cpu] Bit Shuffler (Take 2)

[Michael Riepe <michael@stud.uni-hannover.de>]

On Fri, Sep 28, 2001 at 10:45:56PM +0200, Yann Guidon wrote:
[...]
> > I'm afraid we're hitting the `6 gates' rule with the bit shuffling
> > unit, no matter how we implement it.  Maybe we should add a second
> > stage to the `bitwise' pipeline (shift/rot/bitrev operations).
> 
> it's clear that if it's not fast enough, pipelining is necessary.
> We'll keep the other strategies in stock, so the user can decide
> which version to use, if it synthesises better with its target
> implementation.

Yep.

> However, good sense says that most often used operations must be faster :
> ROL, ROR, SHR, SLR and SHL are the most critical operations.
> It is not "critical" if SDUP takes two cycles instead of one.

Unfortunately, sdup/byterev/mix/expand are so easy to implement that
they only need one cycle, while the bitwise operations are harder :(
A 6-to-64 decoder alone (for the shift count) needs 50% of a 6-gate
F-CPU pipeline stage...

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
*************************************************************
To unsubscribe, send an e-mail to majordomo@seul.org with
unsubscribe f-cpu       in the body. http://f-cpu.seul.org/