Re: [f-cpu] Bit Shuffler (Take 2)

[Michael Riepe <michael@stud.uni-hannover.de>]

On Sat, Sep 29, 2001 at 07:37:08PM +0300, Kim Enkovaara wrote:
> On Sat, 29 Sep 2001, Yann Guidon wrote:
> 
> > > Synplify usually likes as high level descriptions as possible. But I think
> > > that optimizing for speed at this stage is not wise thing to do.
> > how do you tell Synplify to pipeline the multiplier ? and how do you instruct it
> > to provide partial results ?
> 
> Easiest way to do that is to write a*b in the VHDL and add as many
> fliflops after the operation as you need pipeline stages. Then just ask
> the Synplify to balance the registers. In that way it creates very well
> optimized pipelined multiplier. Also if the FPGA architecture includes HW
> multipliers it uses them during the synthesis. In VirtexII architecture
> synplify can't use the internal flipflops of the 18x18 multiplier, but
> those flipflops are not documented or characterized at the monent, but
> they are there.

You may be able to get a 64-bit multiplier by writing `Y <= A * B'
and letting the synthesis tool do the rest, but how do you handle
signed/unsigned multiplication, SIMD chunks and so on?  I doubt that
there is any synthesizer out there who can do that automatically.

[...]
> I think the only way to see the results is to synthesize the results
> yourself and analyze the results from the shematics. It is very difficult
> to analyze the results if the code is not written by yourself.

At least, you need a basic idea how it works (or how it's supposed
to work).

We can't optimize the F-CPU for every possible target -- we neither have
the time nor the synthesis tools.  We can only choose some `generic'
targets, like a random FPGA with 4-input LUTs, write code that is
suitable for them (although not necessarily optimal), and leave the
target-dependent optimization to the implementor.

-- 
 Michael "Tired" Riepe <Michael.Riepe@stud.uni-hannover.de>
 "All I wanna do is have a little fun before I die"
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