gEDA: Icarus verilog synthesis issue

[David Howland <dhowland@xxxxxxxxxxxxx>]

I was hoping someone with knowledge of Icarus could help me out here.

consider this simple circuit:
-----------------------------------------------------
module simple(out, a, b, clk);
input clk;
input [7:0] a, b;
output [7:0] out;
reg [7:0] out;
always @(posedge clk) begin
	out <= (a & b);
end
endmodule
-----------------------------------------------------

why would such a simple circuit fail with this error?
-----------------------------------------------------
simple.v:10: internal error:  not a simple signal? (a[7:0])&(b[7:0])
assertion "d" failed: file "./syn-rules.y", line 196, function "void 
make_DFF_CE(Design*, NetProcTop*, NetEvWait*, NetEvent*, NetExpr*, 
NetAssignBase*)"
-----------------------------------------------------

Thanks for any help,

-d