Re: gEDA: verilog question

[Stephen Williams <steve@icarus.com>]

martin@myri.com said:
> I have looked at the Icarus verilog compiler just out of curiosity. I
> have tried this simple verilog module: 

The part that misses for XNF synthesis is this:

        always @(w or reset) begin ... end

What you are trying to implement there is actually combinational logic.
You can get the always block to synthesize by replacing it with the following:

	wire o_next = reset? 0 : w;

Or better yet:

	always @(posedge clk) o = reset? 1'b0 : a & ~b | ~a & b;

However, I do not deny the fact that my synthesis does not catch your
case and generate the proper code for you. What it misses first is the
anyedge trigger on (w or reset). posedge and negedge are handled better.

I have plans to do full state machine synthesis once I get closer to
completing language coverage.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."