Re: gEDA: verilog metacomments

[Hagen Sankowski <office@anydroid.de>]

Hi all.

Am Mittwoch den, 3. Juli 2002, um 01:16, schrieb Stephen Williams:

> The attributes parsed by the compiler are accessible to code
> generators that use the ivl_target API. Thus, code generators
> can define their own new attributes, if desired. I already used
> this feature to allow the fpga target to accept pin assignments
> from attributes in the source Verilog.

So let me interrupt.

Synopsys as market leader use pragmas in a ugly way. I've seen pragmas 
for Synopsys design compiler and FPGA Express witch dosn't work 
correctly, for instance
Pragma: 'synopsys translate on/off' and 'synthesis on/off'. And there 
are tools ignoring pragmas completly (renoir I know).

Because attributes passed thrue backend tools, metacomments aka pragmas 
doesn't, I strongly recommend the clean way to work with attributes. 
Every time you transfer a project or old source to a new tool, using 
pragmas, you have to translate all vendor specific pragmas. The work is 
yours. Please think about the clean way and code attributes to iverilog 
how -2000 it's offers. Btw attributes are the best style to do pin 
assignments at backend I've ever seen.

I would offer my help and experience as design engineer to form a quite 
nice set of attributes.

Thanks for your attention and have a nice day.

Regards,
Hagen Sankowski