Re: gEDA: Verilog attributes question

[Stephen Williams <steve@icarus.com>]

hamish@debian.org said:
> VHDL has always had attributes -- but translate_off/on comments are
> the only way to skip synthesis on selected parts of the code. 

Because VHDL attributes can be attached to named objects, but not
processes, operators, etc. There is a Verilog attribute syntax
for just about everything. It's actually pretty kool.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
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