Re: gEDA: verilog metacomments

[Stephen Williams <steve@icarus.com>]

john_g@cibolo.com said:
> Would one of you tell us, and especially me, more about attributes
> being a slick way to assign FPGA pins. 

When you are modeling a chip that goes into an FPGA, the top level
module may contain ports that represent the pins of the device.
With Icarus Verilog, you can attach attributes to those ports to
tell place-and-route where (which "PAD") to place those ports.

For example:
        module main(out, in);
            output out;
            input [2:0] in;
            [...]
            $attribute(out, "PAD", "10");
            $attribute(in, "PAD", "20,21,22");
        endmodule

This example uses the Icarus Verilog specific $attribute syntax,
but it can also be done with (* *) attributes.

FPGA Tool chains usually also have a non-Verilog way to express
things like PAD assignments. Xilinx uses constraint files, although
Icarus Verilog can generate constraint files from the attribute
information it pulls from the Verilog source.

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
steve at picturel.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

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