Re: gEDA: verilog metacomments

[Ales Hvezda <ahvezda@seul.org>]

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-- Cut here --
From: Udi Finkelstein <geda-dev@udif.com>

Michael Baxter wrote:
> Icarus Verilog friends,
> 
> Verilog metacomments for synthesis are standard issue, used by all
> synthesis tools. My experience has been that there are more similar than
> different between Synopsys, Synplicity, and Xilinx Synthesis Technology
> (XST), the synthesis tool bundled with the FISE FPGA implementation tools.
> 
> There are differences, yes, and there are semantic issues. For instance,
> most FPGA-oriented synthesis tools do not force you to use parallel case
> directives to build a mux or PLA out out case statements. These later
> generation tools know that you typically aren't being so dumb as to infer

No synthesis tool will ever infer a latch when you want a mux, unless 
you incorrectly specified your mux, i.e.:
1. Did not include all possible case items or did not include a default 
clause.
2. Used an incomplete sensitivity list.

I avoid all uses of full_case and parallel_case and "surprisingly" 
enough, I got my muxes working pretty well without them.

As for synthesis tools being "smart enough" to generate a mux even when 
your verilog code looks like a latch, I would rather say that these 
tools are not smart enough to generates the latches you specified.

> a latch. By the same token, Synopsys cannot assume that you are not, and
> evidently always infers the latch unless you explicitly tell the tool not
> to. But syntax-wise, the Verilog comments are really pretty much the same.

This is not accurate: For example, an incomplete sensitivity list in 
synopsys will NOT generate a latch. it will generate a combinatorial and 
warn about the missing signal in the sensitivity list. latches are 
generated only when some signal assigments appear only in part of your 
code path, i.e.:

if (cond)
   latch <= value;

Udi