gEDA: Re: gEDA-user: gaf and verilog?

[John Griessen <john_g@cibolo.com>]

Hi Dan, Mike,

I'm confused about what Mike says below using words model port....
I have not used the Synopsis smart model library....
Do you get it?

Have you and Mike identified the best place to put a translator into gnetlist?
With an escape char, you would then process the file separately to translate 
it.   Is there some way to build it into gnetlist existing user interface?
It's a highly valuable concept for wroking with existing designs from past 
breadboard methods with few formal specs besides, "It works...", then going 
to a verifiable version before reducing and resimulating that for cost 
reduction and integration projects.   (The kind of projects that have a 
chance of paying the bills!)

John Griessen
================================
On Wednesday 10 July 2002 09:58 pm, mcmahill@mtl.mit.edu wrote:
> that change might be nice.
.
.
  I can probably add the verilog `escape'
> > character to invalid Verilog names if this will help.  What is done
> > commercially for this situtation is to use a pin number to Verilog model
> > port mapping.  When you use the Synopsis smart model library, `.ptm'
> > files are provided with the models to obtain precisely this mapping, for
> > a given package type.  (This happens to be really close to what one of my
> > day jobs is...)
> >
> > --
> > --------------------------------------------------
> >                               Mike Jarabek
> >                                 FPGA/ASIC Designer
> >   http://www.doncaster.on.ca/~mjarabek
> > --------------------------------------------------