Mail Index

• Thread Index

• gEDA: Information about netlist format
  • From: Sriram Ragunathan <sragunat@ececs.uc.edu>
• Re: gEDA: Re: Verilog question wrt expression bit widths
  • From: James Lee <jml@seva.com>
• Re: gEDA: Information about netlist format
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: char_width.c in gEDA-19990516
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: New release scheme in place
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Misc announcements
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: More info on that last development snapshot
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: gnetlist and hierarchy
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: New release scheme in place
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: New release scheme in place
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: More info on that last development snapshot
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: gnetlist and hierarchy
  • From: "Gordon McGregor" <r44957@email.sps.mot.com>
• gEDA: Uploaded geda-symbols 19990601-1 (source all) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded libgeda 19990601-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda 19990601 (source all) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-gschem 19990601-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: new Debian packages
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: More info on that last development snapshot
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: New release scheme in place
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: New release scheme in place
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: gEDA manual
  • From: Andre Malafaya Baptista <Malafaya@milenio3.pt>
• gEDA: gEDA manual
  • From: thi <ttn@mingle.glug.org>
• Re: gEDA: Re: Results from verilog XL
  • From: David Cary <d.cary@ieee.org>
• Re: gEDA: Re: Results from verilog XL
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Re: Results from verilog XL
  • From: stevenwilson <stevenwilson@micron.com>
• gEDA: latest gwave segfaults
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: latest gwave segfaults
  • From: Stephen Tell <tell@cs.unc.edu>
• gEDA: Verilog integers
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: latest gwave segfaults
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: latest gwave segfaults
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: More info on that last development snapshot
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: latest gwave segfaults
  • From: Stephen Tell <tell@cs.unc.edu>
• gEDA: Verilog 19990606 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: latest gwave segfaults
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: Verilog integers
  • From: Michael Baxter <mabaxter@pacbell.net>
• Re: gEDA: Verilog integer bits
  • From: Michael Baxter <mabaxter@pacbell.net>
• Re: gEDA: Verilog integer bits
  • From: Michael Baxter <mabaxter@pacbell.net>
• Re: gEDA: Verilog integers
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Verilog integer bits
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog integer bits
  • From: Michael Baxter <mabaxter@pacbell.net>
• Re: gEDA: Verilog integer bits
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog integer bits
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Re: Verilog integer bits
  • From: James Lee <jml@seva.com>
• gEDA: Re: Verilog integer bits
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Re: Verilog integer bits
  • From: James Lee <jml@seva.com>
• Re: gEDA: Verilog 19990606 snapshot
  • From: Stephen Tell <tell@cs.unc.edu>
• Re: gEDA: Re: Verilog integer bits
  • From: Stephen Williams <steve@icarus.com>
• gEDA: VCD viewers
  • From: Stephen Williams <steve@icarus.com>
• gEDA: New symbols
  • From: José Daniel Muñoz Frías <daniel@dea.icai.upco.es>
• Re: gEDA: VCD viewers
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: VCD viewers
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: VCD viewers
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: VCD viewers
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: New symbols
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: More info on that last development snapshot
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: gEDA manual
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: New release scheme in place
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Alternative slot description format?
  • From: Roger Williams <roger@coelacanth.com>
• gEDA: Alternative slot description format?
  • From: thi <ttn@mingle.glug.org>
• gEDA: Displaying component information?
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: More info on that last development snapshot
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Alternative slot description format?
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Alternative slot description format?
  • From: Rick Munden <munden@acuson.com>
• Re: gEDA: Alternative slot description format?
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Alternative slot description format?
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Alternative slot description format?
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Displaying component information?
  • From: "Gordon McGregor" <r44957@email.sps.mot.com>
• gEDA: 19990610 snapshot released
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: More info on that last development snapshot
  • From: Roger Williams <roger@coelacanth.com>
• gEDA: Icarus Verilog 19990612 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Alternative slot description format?
  • From: thi <ttn@mingle.glug.org>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Alternative slot description format?
  • From: Roger Williams <roger@coelacanth.com>
• Again ... gEDA: Icarus Verilog 19990612 snapshot
  • From: Stephen Williams <steve@icarus.com>
• gEDA: unsubscribe how?Lost majordomo
  • From: jos runarko <josr0633@cetus.zrz.TU-Berlin.DE>
• Re: gEDA: More info on that last development snapshot
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Symbols Power Pins and Signal Directions
  • From: David Cary <d.cary@ieee.org>
• gEDA: VHDL mailing list?
  • From: David Cary <d.cary@ieee.org>
• Re: gEDA: VHDL mailing list?
  • From: dmartin@clifton-labs.com (Dale E. Martin)
• Re: gEDA: Power nets (first RFC)
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: unsubscribe how?Lost majordomo
  • From: Stefan Petersen <spe@stacken.kth.se>
• gEDA: Clipboard
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Alternative slot description format?
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• RE: gEDA: Power nets (first RFC)
  • From: Mozur Matt <Matt.Mozur@EMG.SMS.SIEMENS.COM>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Ansel Sermersheim <agserm@netwizards.net>
• RE: gEDA: Re: Results from verilog XL
  • From: David Cary <d.cary@ieee.org>
• RE: gEDA: Re: Results from verilog XL
  • From: thi <ttn@mingle.glug.org>
• gEDA: geda-dev@seul.org
  • From: Peter Cooper <pcc@cs.york.ac.uk>
• Re: gEDA: Re: Verilog integer bits
  • From: David Cary <d.cary@ieee.org>
• Re: gEDA: Re: Results from verilog XL
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Re: Verilog integer bits
  • From: Jeff McNeal <jmcneal@level1.com>
• gEDA: A GPL Verilog "lint" advocate
  • From: "Brad Martin P.E." <brad@nshore.com>
• Re: gEDA: Re: Verilog integer bits
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: A GPL Verilog "lint" advocate
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Re: Results from verilog XL
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Warnings from ivl
  • From: Jeff McNeal <jmcneal@level1.com>
• RE: gEDA: Warnings from ivl
  • From: stevenwilson <stevenwilson@micron.com>
• RE: gEDA: Warnings from ivl
  • From: stevenwilson <stevenwilson@micron.com>
• gEDA: open hardware database
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• Re: gEDA: Warnings from ivl
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Warnings from ivl
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: open hardware database
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: open hardware database
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• gEDA: Savant version 1.01 available
  • From: dmartin@clifton-labs.com (Dale E. Martin)
• Re: gEDA: Warnings from ivl
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Warnings from ivl
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Power nets (first RFC)
  • From: "Andrew M. Dyer" <adyer@enteract.com>
• RE: gEDA: Re: Results from verilog XL
  • From: stevew <stevew@home.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• RE: gEDA: Power nets (first RFC)
  • From: Mozur Matt <Matt.Mozur@EMG.SMS.SIEMENS.COM>
• Re: gEDA: Warnings from ivl
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: New symbols
  • From: José Daniel Muñoz Frías <daniel@dea.icai.upco.es>
• [Fwd: gEDA: New symbols]
  • From: José Daniel Muñoz Frías <daniel@dea.icai.upco.es>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Warnings from ivl
  • From: stevew <stevew@home.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• RE: gEDA: Power nets (first RFC)
  • From: Mozur Matt <Matt.Mozur@EMG.SMS.SIEMENS.COM>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: open hardware database
  • From: Stefan Petersen <spe@stacken.kth.se>
• gEDA: gmos version
  • From: "Ed Carter (r47652)" <r47652@email.sps.mot.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: "Andrew M. Dyer" <adyer@enteract.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: gmos version
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: [Fwd: gEDA: New symbols]
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: open hardware database
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Andrew Dyer <adyer@enteract.com>
• Re: gEDA: Power nets (first RFC)
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• gEDA: Icarus Verilog 19990619 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog 19990619 snapshot
  • From: Michael Baxter <mabaxter@pacbell.net>
• ivl and XNF: (Re: gEDA: Icarus Verilog 19990619 snapshot)
  • From: Stephen Williams <steve@icarus.com>
• gEDA: ivl XNF w/ patch
  • From: Stephen Williams <steve@icarus.com>
• gEDA: ACS (Al's Circuit Simulator) 0.23 uploaded
  • From: Al Davis <aldavis@ieee.org>
• Re: gEDA: Power nets (first RFC)
  • From: David Cary <d.cary@ieee.org>
• RE: gEDA: Power nets (first RFC)
  • From: thi <ttn@mingle.glug.org>
• RE: gEDA: Warnings from ivl
  • From: stevenwilson <stevenwilson@micron.com>
• gEDA: ivl to XNF
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Power nets (first RFC)
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Power nets (first RFC)
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• gEDA: Character Set for Names and Labels
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Icarus Verilog 19990619 snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: Character Set for Names and Labels
  • From: Roger Williams <roger@coelacanth.com>
• RE: gEDA: Power nets (first RFC)
  • From: stevenwilson <stevenwilson@micron.com>
• RE: gEDA: Icarus Verilog 19990619 snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990619 snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• RE: gEDA: Power nets (first RFC)
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990619 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: ACS (Al's Circuit Simulator) 0.23 uploaded
  • From: Manu Rouat <emmanuel.rouat@wanadoo.fr>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Character Set for Names and Labels
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: ACS (Al's Circuit Simulator) 0.23 uploaded
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Character Set for Names and Labels
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Icarus Verilog 19990619 snapshot
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power nets (first RFC)
  • From: Laurin Blacken <laurin@novationinc.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• gEDA: comment patch
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Power nets (first RFC)
  • From: Thomas Dean <tomdean@ix.netcom.com>
• RE: gEDA: Power nets (first RFC)
  • From: Mozur Matt <Matt.Mozur@EMG.SMS.SIEMENS.COM>
• Re: gEDA: Power nets (first RFC)
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• Re: gEDA: Power nets (first RFC)
  • From: Roger Williams <roger@coelacanth.com>
• gEDA: CERTIFIED GIFTED PSYCHICS
  • From: jimsmith@aol.com
• gEDA: CERTIFIED GIFTED PSYCHICS
  • From: jimsmith@aol.com
• Re: gEDA: ACS (Al's Circuit Simulator) 0.23 uploaded
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: vpp preprocessor for ivl - `define not working?
  • From: Stephen Tell <tell@cs.unc.edu>
• gEDA: Re: vpp preprocessor for ivl - `define not working?
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Re: vpp preprocessor for ivl - `define not working?
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Re: vpp preprocessor for ivl - `define not working?
  • From: Steve Wilson <stevew@home.com>
• gEDA: Verilog Netlister 19990629 Released
  • From: Mike Jarabek <mjarabek@playground.net>
• gEDA: OrCAD imports to gEDA
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: OrCAD imports to gEDA
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: OrCAD imports to gEDA
  • From: Stephen Williams <steve@icarus.com>