Mail Index
- gEDA-dev: Help in apply SoC2007
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Re: Google summer of code
- Icarus Verilog Graffiti; was Re: gEDA-dev: Re: Google summer of code
- Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code
- Re: Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code
- Re: Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: Google SOC suggestion for students
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: gnetman inspired libgeda datastructures
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: Re: VHDL as a file format
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: Re: VHDL as a file format
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Re: VHDL as a file format
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Re: VHDL as a file format
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Re: Regarding SoC application
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Help in apply SoC2007
- gEDA-dev: New gnucap development snapshot 2007-03-29
- Re: gEDA-dev: geda-doc package has some redundant files
- Re: gEDA-dev: Pinning down libgeda
- Re: gEDA-dev: sch2svg converter needed
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: debugging Gtk-WARNING **:Invalid input string
- gEDA-dev: More GSoC project ideas added
- Re: gEDA-dev: More GSoC project ideas added
- Re: gEDA-dev: Patches on sourceforge
- Re: gEDA-dev: Souce Contreol of big architectural projects
- Re: gEDA-dev: SoC Hopeful
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- gEDA-dev: Google summer of code
- gEDA-dev: topological routing path search algorithms
- Re: gEDA-dev: topological routing path search algorithms
- Re: gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)
- RE: gEDA-dev: Souce Contreol of big architectural projects inGoogleSoC....
- gEDA-dev: SoC Hopeful
- gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: EDIF docs?
- From: Carlos Nieves Ónega
- Re: gEDA-dev: Revised symbol license text
- gEDA-dev: My multiple footprint plan
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: Pinning down libgeda
- Re: gEDA-dev: Google summer of code
- gEDA-dev: google SOC
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)
- gEDA-dev: PCB: escape key
- Re: gEDA-dev: PCB: escape key
- gEDA-dev: PCB: gtk testers needed
- gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: PCB: gtk testers needed
- gEDA-dev: debugging Gtk-WARNING **:Invalid input string
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- gEDA-dev: Google SOC suggestion for students
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: C question
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: Noscreen branch
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google summer of code
- gEDA-dev: pcb bug 1651335
- Re: gEDA-dev: PCB: escape key
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: debugging Gtk-WARNING **:Invalid input string
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: topological routing path search algorithms
- Re: gEDA-dev: topological routing path search algorithms
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: Re: VHDL as a file format
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- gEDA-dev: x_compselect.c
- Re: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)
- gEDA-dev: Re: gEDA-user: scons
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: Google summer of code
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)
- Re: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)
- Re: gEDA-dev: PCB: escape key
- Re: gEDA-dev: PCB: escape key
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: sch2svg converter needed
- Re: gEDA-dev: Hi... question about refdes_renum
- gEDA-dev: hierarchy and multipart symbols (several with same refdes)
- Re: gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: Further thoughts on Parts Manager
- Re: gEDA-dev: Further thoughts on Parts Manager
- gEDA-dev: new wiki section added for approval by Kurt
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: gnetman inspired libgeda datastructures
- Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: proposed changes to drag on PCB
- Re: gEDA-dev: PCB: escape key
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: Further thoughts on Parts Manager
- Re: gEDA-dev: More GSoC project ideas added
- gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- gEDA-dev: New member
- gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Regarding SoC application
- Re: gEDA-dev: Peripheral SoC Project ideas
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Pinning down libgeda
- Re: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (was gEDA-user: PCB Element for a Molex 71661-2068?)
- gEDA-dev: Souce Contreol of big architectural projects in Google SoC....
- gEDA-dev: Peripheral SoC Project ideas
- RE: gEDA-dev: Souce Contreol of big architectural projects in GoogleSoC....
- Re: gEDA-dev: Peripheral SoC Project ideas
- gEDA-dev: Patches on sourceforge
- Re: gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: Google SoC Announcement
- Re: gEDA-dev: Google SoC Announcement
- RE: gEDA-dev: Souce Contreol of big architectural projects inGoogleSoC....
- Re: gEDA-dev: Revised symbol license text
- gEDA-dev: Further thoughts on Parts Manager
- Re: gEDA-dev: Further thoughts on Parts Manager
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: SoC Hopeful
- gEDA-dev: gnetman inspired libgeda datastructures
- Re: gEDA-dev: gnetman inspired libgeda datastructures
- gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: gnetman inspired libgeda datastructures
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: Hidden Nets Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- gEDA-dev: Noscreen branch
- Re: gEDA-dev: Noscreen branch
- Re: gEDA-dev: Bug reports for gattrib
- Re: gEDA-dev: proposed changes to drag on PCB
- gEDA-dev: New wiki page about data structure
- Re: gEDA-dev: Re: gEDA-user: scons
- Re: gEDA-dev: Pinning down libgeda
- Re: gEDA-dev: XML File Formats, hierarchy issues and other rants
- Re: gEDA-dev: Souce Contreol of big architectural projects in GoogleSoC....
- Re: gEDA-dev: XML File Formats, hierarchy issues and other rants
- Re: gEDA-dev: XML File Formats, hierarchy issues and other rants
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: topological routing path search algorithms
- gEDA-dev: Verilog: $fscanf and $sscanf don't correctly report match count
- Re: gEDA-dev: Regarding SoC application
- gEDA-dev: Re: VHDL as a file format
- From: Stephen Brickles using shaun
- gEDA-dev: Re: Icarus Verilog and Xilinx unisim files
- gEDA-dev: Re: Google summer of code
- gEDA-dev: Re: Google summer of code
- gEDA-dev: Re: Icarus Verilog Graffiti; was Re: Re: Google summer of code
- gEDA-dev: Re: Icarus Verilog projects in academic; was Re: Google summer of code
- gEDA-dev: Re: Icarus Verilog and Xilinx unisim files
- gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- gEDA-dev: Re: VHDL, was Re: Hierarchical buses
- gEDA-dev: Re: VHDL as a file format
- gEDA-dev: Re: Verilog: $fscanf and $sscanf don't correctly report match count
- gEDA-dev: Re: Regarding SoC application
- gEDA-dev: Re: EDIF docs?
- gEDA-dev: Bug reports for gattrib
- Re: gEDA-dev: Pinning down libgeda
- Re: gEDA-dev: Pinning down libgeda
- Re: gEDA-dev: April code sprint announcement!
- Re: gEDA-dev: Hi... question about refdes_renum
- gEDA-dev: gschem Write PNG output Issue
- Re: gEDA-dev: Hi... question about refdes_renum
- gEDA-dev: XML File Formats, hierarchy issues and other rants
- gEDA-dev: DRC
- gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: topological routing path search algorithms
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Hidden Nets Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: New diagram (attempt at UML)
- Re: gEDA-dev: Noscreen branch
- Re: gEDA-dev: google SOC
- Re: gEDA-dev: Google summer of code
- gEDA-dev: Call for Google SoC Mentors!
- gEDA-dev: April code sprint announcement!
- Re: gEDA-dev: PCB: escape key
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: Hi... question about refdes_renum
- Re: gEDA-dev: XML File Formats, hierarchy issues and other rants
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- Re: gEDA-dev: XML File Formats, hierarchy issues and other rants
- gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: GPL clarification text -- please review & comment/flame!
- Re: gEDA-dev: Rant on GPL confussion in regards to geda symbols
- gEDA-dev: Revised symbol license text
- Re: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: SoC Hopeful
- Re: gEDA-dev: gnetman inspired libgeda datastructures
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: Bug reports for gattrib
- Re: gEDA-dev: gnetman inspired libgeda datastructures
- Re: gEDA-dev: waveform viewer, collected some notes in the wiki
- Re: gEDA-dev: Re: VHDL as a file format
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- Re: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- RE: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)
- RE: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter(was gEDA-user: PCB Element for a Molex 71661-2068?)
- RE: gEDA-dev: PCB - XY values of centrioid in BOM/DXF exproter (wasgEDA-user: PCB Element for a Molex 71661-2068?)
- RE: gEDA-dev: Souce Contreol of big architectural projects in GoogleSoC....
- RE: gEDA-dev: GPL clarification text -- please review & comment/flame!
- RE: gEDA-dev: SoC Hopeful
- RE: gEDA-dev: Souce Contreol of big architectural projects
- RE: gEDA-dev: SoC: Gerber, DRC, gsch2pcb and D-BUS
- RE: gEDA-dev: Revised symbol license text
- RE: gEDA-dev: Revised symbol license text
- Re: gEDA-dev: google SOC
- From: Timothy Normand Miller
- Re: gEDA-dev: Google summer of code
- From: Timothy Normand Miller
- Re: Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code
- From: Timothy Normand Miller
- Re: Icarus Verilog projects in academic; was Re: gEDA-dev: Google summer of code
- From: Timothy Normand Miller
- gEDA-dev: EDIF docs?
- From: Timothy Normand Miller
- gEDA-dev: Patch for "click on focus for zoom" bug
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- Re: VHDL, was Re: gEDA-dev: Hierarchical buses
- gEDA-dev: Icarus Verilog and Xilinx unisim files
- Re: gEDA-dev: Re: Icarus Verilog and Xilinx unisim files
- Re: gEDA-dev: Re: Icarus Verilog and Xilinx unisim files
- Re: gEDA-dev: Google summer of code
- gEDA-dev: sch2svg converter needed
- Re: gEDA-dev: sch2svg converter needed
- gEDA-dev: waveform viewer, collected some notes in the wiki
- Re: gEDA-dev: topological routing path search algorithms
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