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Re: gEDA: parallel verilog

From: John Sheahan <jrsheahan@optushome.com.au>
Subject: gEDA: parallel verilog
Date: Sat, 24 May 2003 08:40:18 +1000

> Does anyone have thoughts they can share on the 
> practicality of accelerating verilog simulation 
> for a single test bench by distributing the job over 
> multiple CPUs?

Well... this sounds exactly like the kind of thing that Savant does for VHDL.
Take a look at it...

Cheers,
Magnus