Re: gEDA: Logic synthesis tool

[Tim Freedom <tim_freedom@yahoo.com>]

Paul Hartke wrote:
> Have a look at Icarus Verilog:  http://icarus.com/eda/verilog/
> Stephen has added some synthesis capabilities.  While the initial support 
> is for Xilinx FPGAs, it could be expanded to target other architectures.

Has anyone looked into breaking those two functions into their own separate
applications with some shared libraries ?  In other words, why not have one
application that simply does simulations (verilog in this case) and one that
does synthesis only ?  Having the two lumped doesn't seem natural (I don't
think too many people would expect to run VCS to simulate and synthesize,
etc).  I would also tend to think that such a move would bring better focus
to both tools, as a full-fledged synthesis option is rather missing.

Anthony J Bybell wrote:
> Translation from an HDL/RTL to a netlist is somewhat straightforward
> and isn't ridiculously difficult.  But that's just the beginning as there
> are other phases downstream:
> 
> 1) Mapping from tech independent gates to a specific technology
> 2) Static timing analysis
> 3) Restructuring to make timing/meet technology constraints
> 4) Ensuring boolean/functional equivalence on remapped logic cones
> etc.

Agreed, so if its straightforward and as Mr Cox noted is 'doable' (at
least to the 80% mark), then why not start an open source project along
those lines ?  I wasn't familiar with OCTTOOLS (version 5.2) and am not
sure of its licensing, but it could prove to be a great starting point.

What do others think ?  Synthesis (along with formal verification) seem
to be the missing pieces of what is out there for those interested in
open source (or free) solutions.

Regards,

 .tf.


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