Re: gEDA: olympus synthesis system?

[Stephen Williams <steve@icarus.com>]

Bill Cox wrote:

> The definition of what I'm calling "RTL level structural" verilog is 
> fuzzy.  What I really mean is the internal structural components built 
> in the front-end tool.  For example, the built-in operators can be 
> represented as individual instances.  There's no need to choose the 
> style of adder, for example, before we get it into a fully incrementally 
> timing-driven netlist database.  At a minimum, all the behavioral 
> process code needs to be replaced with simple assignment statements, and 
> component instantiation.
>
> I'd go into more detail, but if Stephen Williams were to write out this 
> netlist, I'd want him to define the contents.  Verilog operators are a 
> good start, but they might not contain enough expressive power to do the 
> whole job.  Some new component types may need to be defined.  In 
> general, there can't be any high-level language constructs like 
> for-loops, but there can be lower level blocks like RAMs.
The -tfpga -parch=lpm code generator emits LPM 2 1 0 gates in EDIF.
If you want to get at it earlier in the flow, the ivl_target.h header
file defines the API for getting at the design after ivl processing
but before netlist output. It is the API that fpga.tgt and vvp.tgt
use.

It could be better documented, but it is certainly there, just
begging to be exploited.

--
Steve Williams                "The woods are lovely, dark and deep.
steve at icarus.com           But I have promises to keep,
http://www.icarus.com         and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."