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• Re: gEDA: 19990829 development snapshots released : intel RPMS
  • From: Manu Rouat <emmanuel.rouat@wanadoo.fr>
• gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog RFC
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog RFC
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog RFC
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog RFC
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Icarus Verilog todo list
  • From: Stephen Williams <steve@icarus.com>
• gEDA: quiet list?
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: quiet list?
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Netlister broken
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• Re: gEDA: Icarus Verilog todo list
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Netlister broken
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Icarus Verilog todo list
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog todo list
  • From: Andrew Bardsley <bardslea@cs.man.ac.uk>
• RE: gEDA: Netlister broken
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• Re: gEDA: Icarus Verilog todo list
  • From: Arnim Littek <arnim@actrix.gen.nz>
• Re: gEDA: Netlister broken
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Netlister broken
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Icarus Verilog 19990903 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Netlister broken
  • From: Mike Jarabek <mjarabek@playground.net>
• gEDA: Icarus Verilog 0.1 Feature Freeze
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Re: IVL lexical problem/patch
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Moving delay...
  • From: Eric Busta <ewbusta@uswest.net>
• Re: gEDA: Icarus Verilog 0.1 Feature Freeze
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Moving delay...
  • From: Terry Porter <tp@gronk.apana.org.au>
• gEDA: Icarus Verilog web page
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Icarus Verilog web page, redux
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Verilog: empty statements, more tests
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Icarus Verilog 0.1 Feature Freeze
  • From: Guy Hutchison <ghutchis@pacbell.net>
• Re: gEDA: One ore tester!
  • From: "Darin Ingimarson" <darin@k2t.com>
• gEDA: One ore tester!
  • From: Thomas Heidel <theidel@advis.de>
• Re: gEDA: Verilog: empty statements, more tests
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Dumb (g)netlist question.
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Dumb (g)netlist question.
  • From: "Richard G. Munden" <munden@acuson.com>
• Re: gEDA: Dumb (g)netlist question.
  • From: "Andrew M. Dyer" <adyer@enteract.com>
• Re: gEDA: Verilog: empty statements, more tests
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Dumb (g)netlist question.
  • From: Matt Mozur <matt.mozur@flashcom.net>
• Re: gEDA: One more tester!
  • From: Thomas Heidel <theidel@advis.de>
• Re: gEDA: One more tester!
  • From: "Darin Ingimarson" <darin@k2t.com>
• gEDA: Verilog: task arguments
  • From: Peter Monta <pmonta@halibut.imedia.com>
• gEDA: Uploaded geda-gschem 19990829-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-utils 19990829-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-symbols 19990829-1 (source all) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded libgeda 19990829-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-gnetlist 19990829-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda 19990809 (source all) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: Dumb (g)netlist question.
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: debs uploaded
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: Dumb (g)netlist question.
  • From: Laurin Blacken <laurin@novationinc.com>
• gEDA: Verilog: misc. elaboration
  • From: Peter Monta <pmonta@halibut.imedia.com>
• RE: gEDA: Verilog: misc. elaboration
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Verilog: empty statements, more tests
  • From: Guy Hutchison <ghutchis@pacbell.net>
• Re: gEDA: debs uploaded
  • From: Manu Rouat <emmanuel.rouat@wanadoo.fr>
• Re: gEDA: Verilog: misc. elaboration
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Verilog: misc. elaboration
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Verilog: misc. elaboration
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: empty statements, more tests
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Dumb (g)netlist question.
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Dumb (g)netlist question.
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Icarus Verilog web page
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: task arguments
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Verilog: ternary patch
  • From: Peter Monta <pmonta@halibut.imedia.com>
• gEDA: Verilog: ternary test code
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Verilog: ternary patch
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: ternary patch
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Verilog: ternary test code
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: debs uploaded
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Verilog: parse error
  • From: Peter Monta <pmonta@halibut.imedia.com>
• gEDA: Test supervisor RFC
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Test supervisor RFC
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: parse error
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: ternary test code
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: ternary test code
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Verilog: parse error
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Verilog: parse error
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: ternary test code
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Icarus Verilog web page
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Icarus Verilog web page
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Icarus Verilog 19990911 snapshot
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Verilog: integer declarations, string bug?
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Icarus Verilog 19990911 snapshot
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Icarus Verilog 19990911 snapshot
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Power/gnd nets
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Hardware accelerated simulation
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Hardware accelerated simulation
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Hardware accelerated simulation
  • From: Roger Dingledine <arma@mit.edu>
• gEDA: Free prototype board
  • From: "jamil Isma'il khatib" <jamil.khatib@pmail.net>
• Re: gEDA: Hardware accelerated simulation
  • From: dmartin@clifton-labs.com (Dale E. Martin)
• Re: gEDA: Hardware accelerated simulation
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Free prototype board
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Free prototype board
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Free prototype board
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Free prototype board
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Free prototype board
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Free prototype board
  • From: Ales Hvezda <ahvezda@seul.org>
• RE: gEDA: Free prototype board
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• Re: gEDA: Free prototype board
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Free prototype board
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Free prototype board
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• RE: gEDA: Free prototype board
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• gEDA: CVS compilation report
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: CVS compilation report
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: CVS compilation report
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: CVS compilation report
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Power/gnd nets
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Free prototype board
  • From: Stefan Petersen <spe@stacken.kth.se>
• gEDA: Updated verilog compile script and man page 19990913
  • From: Stefan Petersen <spe@stacken.kth.se>
• gEDA: netlisting features
  • From: Matt Ettus <matt@ettus.COM>
• gEDA: Bug in me or ivl??
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Bug in me or ivl??
  • From: Stephen Williams <steve@icarus.com>
• gEDA: my bad...
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: my bad...
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: my bad...
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Updated verilog compile script and man page 19990913
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Allegro Netlister
  • From: Matt Ettus <matt@ettus.com>
• Re: gEDA: Allegro Netlister
  • From: Matt Ettus <matt@ettus.COM>
• gEDA: geda v orcad :-)
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• RE: gEDA: geda v orcad :-)
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: geda v orcad :-)
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• Re: gEDA: geda v orcad :-)
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: geda v orcad :-)
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: geda v orcad :-)
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• RE: gEDA: geda v orcad :-)
  • From: Matt Ettus <matt@ettus.com>
• Re: gEDA: geda v orcad :-)
  • From: Matt Ettus <matt@ettus.com>
• gEDA: Library Preview
  • From: salman sheikh <ssheikh@erols.com>
• Re: gEDA: geda v orcad :-) (fwd)
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: geda v orcad :-)
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Updated verilog compile script and man page 19990913
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Bug in me or ivl??
  • From: Stefan Petersen <spe@stacken.kth.se>
• gEDA: PCB netlist generation???
  • From: Stefan Petersen <spe@stacken.kth.se>
• gEDA: scheme gurus out there?
  • From: Matt Ettus <matt@ettus.COM>
• gEDA: scheme gurus out there?
  • From: thi <ttn@mingle.glug.org>
• Re: gEDA: Bug in me or ivl??
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: PCB netlist generation???
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Updated verilog compile script and man page 19990913
  • From: Stephen Williams <steve@icarus.com>
• gEDA: longstanding bug
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Sparc's core opensourced ? NOT!
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Sparc's core opensourced ? NOT!
  • From: Matthew van de Werken <m.vandewerken@cat.csiro.au>
• Re: gEDA: Sparc's core opensourced ? NOT!
  • From: Matt Ettus <matt@ettus.COM>
• gEDA: Ask and ye shall receive
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Ask and ye shall receive
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: geda v orcad :-)
  • From: Mike Jarabek <mjarabek@playground.net>
• Re: gEDA: longstanding bug
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Ask and ye shall receive
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Updated verilog compile script and man page 19990913
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Ask and ye shall receive
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Library Preview
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: netlisting features
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: netlisting features
  • From: Matt Ettus <matt@ettus.com>
• Re: gEDA: Free prototype board
  • From: Hamish Moffatt <hamish@rising.com.au>
• Re: gEDA: Sparc's core opensourced ? NOT!
  • From: Steve Wilson <stevew@home.com>
• gEDA: Scheme API
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: PCB netlist generation???
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: PCB netlist generation???
  • From: Reinhard Kotucha <reinhard@kammer.uni-hannover.de>
• gEDA: Bug in gnetlist??????????
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: PCB netlist generation???
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: PCB netlist generation???
  • From: Reinhard Kotucha <reinhard@kammer.uni-hannover.de>
• Re: [LONG] Re: gEDA: netlisting features
  • From: paulr <reichp@ameritech.net>
• Re: gEDA: Bug in gnetlist??????????
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: Icarus Verilog 19990915 snapshot
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Newbie hello
  • From: "Adam 'WeirdArms' Wiggins" <awiggins@cse.unsw.edu.au>
• Re: gEDA: Newbie hello
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Newbie hello
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• Re: gEDA: Newbie hello
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Newbie hello
  • From: "Adam 'WeirdArms' Wiggins" <awiggins@cse.unsw.edu.au>
• Re: gEDA: Newbie hello
  • From: "Adam 'WeirdArms' Wiggins" <awiggins@cse.unsw.edu.au>
• Re: gEDA: Newbie hello
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• Re: gEDA: Newbie hello
  • From: "Adam 'WeirdArms' Wiggins" <awiggins@cse.unsw.edu.au>
• Re: gEDA: Bug in gnetlist??????????
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Ask and ye shall receive
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Dumb (g)netlist question.
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Updated verilog compile script and man page 19990913
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Bug in me or ivl??
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Ask and ye shall receive
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Bug in gnetlist??????????
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Newbie hello
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: problems compiling guile
  • From: Reinhard Kotucha <reinhard@kammer.uni-hannover.de>
• Re: gEDA: Newbie hello
  • From: Rick Munden <munden@acuson.com>
• Re: gEDA: Newbie hello
  • From: Jamil Khatib <khatib@ieee.org>
• Re: gEDA: Bug in gnetlist??????????
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Bug in gnetlist??????????
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: problems compiling guile
  • From: Reinhard Kotucha <reinhard@kammer.uni-hannover.de>
• gEDA: Big Symbol
  • From: "jamil Isma'il khatib" <jamil.khatib@pmail.net>
• Re: gEDA: Big Symbol
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Big Symbol
  • From: Erik de Castro Lopo <erikd@zip.com.au>
• Re: gEDA: Big Symbol
  • From: Matt Ettus <matt@ettus.com>
• Re: gEDA: Big Symbol
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Big Symbol
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Big Symbol
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Big Symbol
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Big Symbol
  • From: Matt Ettus <matt@ettus.com>
• Re: gEDA: Big Symbol
  • From: Matt Ettus <matt@ettus.com>
• Re: gEDA: Big Symbol
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: 1MB SIMM symbol
  • From: Marcel van de Vusse <mvusse@bright.net>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• gEDA: 19990919 development snapshots released
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: 19990919 development snapshots released
  • From: Jeff McNeal <jmcneal@level1.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog 19990915 snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Newbie hello
  • From: Al Davis <aldavis@ieee.org>
• gEDA: CVS compile
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: CVS compile
  • From: Ales Hvezda <ahvezda@seul.org>
• RE: gEDA: CVS compile
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• Re: gEDA: CVS compile
  • From: Matt Ettus <matt@ettus.COM>
• gEDA: Oldie hello
  • From: Magnus Danielson <cfmd@swipnet.se>
• gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• RE: gEDA:Another Newbie
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stefan Petersen <spe@stacken.kth.se>
• RE: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• gEDA: Yet another verilog script and man page
  • From: Stefan Petersen <spe@stacken.kth.se>
• RE: gEDA: Icarus Verilog 19990915 snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• RE: gEDA:Another Newbie
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• RE: gEDA: Yet another verilog script and man page
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990915 snapshot
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog 19990915 snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: 19990919 development snapshots released
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: 1MB SIMM symbol
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: Yet another verilog script and man page
  • From: Stephen Williams <steve@icarus.com>
• gEDA: bug in gschem 19990919
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• Re: gEDA:Another Newbie
  • From: Bas Gieltjes <S.Gieltjes@ITS.TUDelft.nl>
• gEDA: VHDL backend to gnetlist
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA:Another Newbie
  • From: Mike Jarabek <mjarabek@playground.net>
• gEDA: Icarus Verilog 19990922 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• Re: gEDA: Icarus Verilog 19990922 Snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• RE: gEDA:Another Newbie
  • From: "Mike Jarabek" <mjarabek@nortelnetworks.com>
• gEDA: gschem howto
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• Re: gEDA: gschem howto
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: gschem howto
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• gEDA: convert_sym hack
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• Re: gEDA:Another Newbie
  • From: Stefan Petersen <spe@stacken.kth.se>
• Re: gEDA:Another Newbie
  • From: Bas Gieltjes <S.Gieltjes@ITS.TUDelft.nl>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: VHDL backend to gnetlist
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: VHDL backend to gnetlist
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• gEDA: Uploaded geda 19990919 (source all) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-gsymcheck 19990919-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-gschem 19990919-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-utils 19990919-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-symbols 19990919-1 (source all) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded libgeda 19990919-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: Uploaded geda-gnetlist 19990919-1 (source i386) to geda
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: new debs uploaded
  • From: Hamish Moffatt <hamish@rising.com.au>
• gEDA: ivl and ivltests
  • From: Jung Pyo Hong <hong@usa.acsys.com>
• RE: gEDA: ivl and ivltests
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: ivl and ivltests
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: ivl and ivltests
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: ivl and ivltests
  • From: Jung Pyo Hong <hong@usa.acsys.com>
• gEDA: ivl_tests
  • From: Jung Pyo Hong <hong@usa.acsys.com>
• Re: gEDA: ivl_tests
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: ivl_tests
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: ivl_tests
  • From: Jung Pyo Hong <hong@usa.acsys.com>
• Re: gEDA: ivl_tests
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Open Source PCB Tools Survey - take 2
  • From: Braddock Gaskill <braddock@gaffney-kroese.com>
• Re: gEDA: ivl and ivltests
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA: new debs uploaded
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• Re: gEDA:Another Newbie
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: RFC on new component model for gEDA
  • From: Darin Ingimarson <darin@k2t.com>
• Re: gEDA: RFC on new component model for gEDA
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: RFC on new component model for gEDA
  • From: Matt Ettus <matt@ettus.com>
• gEDA: Verilog: repeat-concatenation
  • From: Peter Monta <pmonta@halibut.imedia.com>
• gEDA: netlist .scm files howto
  • From: "jamil Isma'il khatib" <jamil.khatib@pmail.net>
• Re: gEDA:Another Newbie
  • From: Thepthai Tabtieng <tabtieng@lsil.com>
• gEDA: Interesting IDE for verilog!
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: more verilog tools
  • From: Steve Wilson <stevew@home.com>
• Re: gEDA: RFC on new component model for gEDA
  • From: "Darin Ingimarson" <darin@k2t.com>
• RE: gEDA: Verilog: repeat-concatenation
  • From: stevenwilson <stevenwilson@micron.com>
• gEDA: Cool RF Stuff
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: netlist .scm files howto
  • From: Matt Ettus <matt@ettus.COM>
• gEDA: set-netlist-mode
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: RFC on new component model for gEDA
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: Cool RF Stuff
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: netlist .scm files howto
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA:Another Newbie
  • From: Bas Gieltjes <S.Gieltjes@ITS.TUDelft.nl>
• Re: gEDA: netlist .scm files howto
  • From: Mike Jarabek <mjarabek@playground.net>
• Re: gEDA: ivl and ivltests
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: repeat-concatenation
  • From: Stephen Williams <steve@icarus.com>
• gEDA: New gwave - 19990927
  • From: Stephen Tell <tell@cs.unc.edu>
• Re: gEDA: Verilog: repeat-concatenation
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: set-netlist-mode
  • From: Ales Hvezda <ahvezda@seul.org>
• gEDA: more verilog tools
  • From: G.Seaman@westminster.ac.uk (Graham Seaman)
• gEDA: Cynlib
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Cynlib
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Cynlib
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Cynlib
  • From: thi <ttn@mingle.glug.org>
• Re: gEDA: RFC on new component model for gEDA
  • From: Matt Ettus <matt@ettus.COM>
• Re: gEDA: Cynlib
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: RFC on new component model for gEDA
  • From: "Darin Ingimarson" <darin@k2t.com>
• Re: gEDA: Cynlib
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Cynlib
  • From: seamang@mboxhost (Graham Seaman)
• Re: gEDA: Cynlib
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Cynlib
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Further thougth on adaption to VHDL et al
  • From: Magnus Danielson <cfmd@swipnet.se>
• gEDA: Re: Further thougth on adaption to VHDL et al
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: Further thougth on adaption to VHDL et al
  • From: Colin Marquardt <colin.marquardt@gmx.de>
• Re: gEDA: Further thougth on adaption to VHDL et al
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Cynlib
  • From: dmartin@clifton-labs.com (Dale E. Martin)
• Re: gEDA: Cynlib
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: Cynlib
  • From: seamang@mboxhost (Graham Seaman)
• Re: gEDA: Cynlib
  • From: Magnus Danielson <cfmd@swipnet.se>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Cynlib
  • From: dmartin@clifton-labs.com (Dale E. Martin)
• gEDA: Verilog vs. AIRE
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Cynlib
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Icarus Verilog code generators
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Gatelevel C++ library
  • From: Rainer Dorsch <rainer@rainer.informatik.uni-stuttgart.de>
• gEDA: RFC on new component model for gEDA
  • From: thi <ttn@mingle.glug.org>
• Re: gEDA: Verilog vs. AIRE
  • From: dmartin@clifton-labs.com (Dale E. Martin)
• Re: gEDA: Verilog vs. AIRE
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog 19990928 Snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stefan Thiede <Stefan.Thiede@sv.sc.philips.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog 19990928 Snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Icarus Verilog 19990928 Snapshot
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Icarus Verilog 19990928 Snapshot
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: simulation startup?
  • From: Steve Wilson <stevew@home.com>
• gEDA: CVS Access to Icarus Verilog
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Gatelevel C++ library
  • From: Rainer Dorsch <rainer@rainer.informatik.uni-stuttgart.de>
• Re: gEDA: CVS Access to Icarus Verilog
  • From: Peter Monta <pmonta@halibut.imedia.com>
• gEDA: Verilog: nested tasks
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: CVS Access to Icarus Verilog
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: nested tasks
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: nested tasks
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Cynlib vs. reality
  • From: thi <ttn@mingle.glug.org>
• gEDA: Cynlib vs. reality
  • From: Stephen Williams <steve@icarus.com>
• gEDA: Verilog: simulation startup?
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Verilog: simulation startup?
  • From: Stephen Williams <steve@icarus.com>
• RE: gEDA: Verilog: simulation startup?
  • From: stevenwilson <stevenwilson@micron.com>
• Re: gEDA: Verilog: simulation startup?
  • From: Stephen Williams <steve@icarus.com>
• Re: gEDA: Verilog: simulation startup?
  • From: Peter Monta <pmonta@halibut.imedia.com>
• Re: gEDA: Verilog: simulation startup?
  • From: Peter Monta <pmonta@halibut.imedia.com>
• gEDA: Patches to utils convert_sym
  • From: Mike Jarabek <mjarabek@playground.net>
• Re: gEDA: Verilog: nested tasks
  • From: Stephen Williams <steve@icarus.com>