RE: gEDA: Icarus Verilog RFC

[stevenwilson <stevenwilson@micron.com>]

>From: Stefan Thiede [mailto:Stefan.Thiede@sv.sc.philips.com]

>stuff deleted -
> Ranges in parameter definition are not supported.
>   These might not be in the standart, but are supported by Verilog-XL
>   and synopsys, so they're in the "unofficial" defacto standard and
>   widely used.
> Sorry, `timescale not supported.
> Sorry, disable statements not supported.
> Sorry, procedural continuous assign not supported.
> warning -- casex not properly supported, using case.
> // synopsys translate_on
> // synopsys translate_off
>   are widely used

I'd agree with the entire list EXCEPT the last two. These
are synopsys directives that will have an OVI equivalent
for synthesis - not simulation. Further -they're in comments
as far as IVL (simulation side) is considered so they're
don't cares.  For that matter - it might even be a matter of
copyright violation or other silliness - They've gone after
Cadence for less! So let's avoid anything with a proprietary
content - like the above.

My two cents worth.

Steve Wilson