Re: gEDA: Icarus Verilog RFC

[Stephen Williams <steve@icarus.com>]

pmonta@halibut.imedia.com said:
> No, it's a newly-open-sourced C++-meets-HDL thing.  Interesting, but
> asking a synthesis tool to look at C++ seems daunting. 

Daunting, maybe even stupid:-) Actually, I've seen a few tools like
this. They basically define a class library that allows one to specify
structure, then the synthesis and simulation are made to happen by
calling magic mains.

Anyhow C++ is horribly ill-suited to the task of specifying hardware.
There is a reason, for example, that local registers in functions and
tasks are "static" in verilog.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
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http://www.picturel.com       And lines to code before I sleep."