Re: gEDA: Verilog: empty statements, more tests

[Steve Wilson <stevew@home.com>]

Hmm - well I sent Steve some tests on case statements
this weekend that should have this covered. I haven't 
run it against IVL yet, just veriwell. 

Steve - let me know if these are indeed caught by the
case tests! I explicitly look for that case.

Peter - I'm a little confused by your question.

If you have a module I/O port that lists a vector port, then
that port has it's width defined in the I/O declaration. So 
unless it is later specified as a reg later in them module, 
it's a wire of that vector width.

If you are talking about the case where  you 
instantiate a module with a named port: Something like

module main ();
...

module mymodule ( .A(input_A),.B(output_B));

Where mymodule has a vector declaration, if you don't have 
a prior statement of:

wire [6:0] input_A, output_B;  

Then these will assume a single bit width.  So you can implicitly
declare them but you probably won't get what you want.  Did I understand
the question correctly?

Steve Wilson
On Mon, 06 Sep 1999, you wrote:
> >%_This small patch fixes empty statements in case items and
> conditionals.  A statement_opt is also used in wait statments
> and tasks, so it might be good to check those for the same bug.
> 
> Attached are some more trivial test files (also one for extended
> identifiers).  VCS passes them all.
> 
> Is it legal to implicity declare a wire using a named port
> within a module instantiation?  This construct occurs in
> some code, but I haven't chased the grammar; VCS accepts it
> though, hm.
> 
> Cheers,
> Peter Monta   pmonta@imedia.com