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Re: gEDA: Verilog: empty statements, more tests

To: geda-dev@geda.seul.org
Subject: Re: gEDA: Verilog: empty statements, more tests
From: Steve Wilson <stevew@home.com>
Date: Wed, 8 Sep 1999 11:43:59 -0700
Delivery-Date: Tue Sep 7 23:34:16 1999
Delivery-Date: Tue, 07 Sep 1999 23:36:07 -0400
Organization: Amateur Station KA6S
References: <199909080220.TAA28714@icarus.com>
Reply-To: geda-dev@seul.org
Sender: owner-geda-dev@seul.org

On Tue, 07 Sep 1999, you wrote:
>stuff deleted.
> 
> On the other hand, I think that "b" may be implicitly declared, as it
> is not a port but an internal net or register. If it is implicit, it is
> a wire with width 1.

That's what I tried to say ;-)

Steve
> -- 
> Steve Williams                "The woods are lovely, dark and deep.
> steve@icarus.com              But I have promises to keep,
> steve@picturel.com            and lines to code before I sleep,
> http://www.picturel.com       And lines to code before I sleep."

References:
- Re: gEDA: Verilog: empty statements, more tests
  - From: Stephen Williams <steve@icarus.com>

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