gEDA: Verilog: task arguments

[Peter Monta <pmonta@halibut.imedia.com>]

While they're easy to work around, I thought I'd mention that the
following task-argument constructs aren't handled (segfaults):

module main;

task foo;
input a;
integer a;
begin
  $display("%d",a);
end
endtask

initial
  foo(30);

endmodule
------------------------------
module main;

task foo;
input a;
reg [10:0] a;
begin
  $display("%d",a);
end
endtask

initial
  foo(30);

endmodule

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.