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RE: gEDA: Verilog: misc. elaboration

To: "'geda-dev@geda.seul.org'" <geda-dev@geda.seul.org>
Subject: RE: gEDA: Verilog: misc. elaboration
From: stevenwilson <stevenwilson@micron.com>
Date: Wed, 8 Sep 1999 10:19:26 -0600
Delivery-Date: Wed Sep 8 13:22:00 1999
Delivery-Date: Wed, 08 Sep 1999 13:23:52 -0400
Reply-To: geda-dev@seul.org
Sender: owner-geda-dev@seul.org

Peter - thanks for the list - along with the 
tests for tasks.  I'll ensure that these get
covered in the test suite!

Steve Wilson

-----Original Message-----
From: Peter Monta [mailto:pmonta@halibut.imedia.com]
Sent: Wednesday, September 08, 1999 8:45 AM
To: geda-dev@geda.seul.org
Subject: gEDA: Verilog: misc. elaboration

Briefly, some things not yet supported by elaboration:

 - nested tasks (though there does seem to be scoping stuff in pform*.cc)
 - mem[x] <= y (though mem[x] = y is okay)
 - if (n) blah; where n is an integer---can't set width to 1

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.

Follow-Ups:
- Re: gEDA: Verilog: misc. elaboration
  - From: Stephen Williams <steve@icarus.com>

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