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Re: gEDA: Verilog: ternary patch

To: geda-dev@geda.seul.org
Subject: Re: gEDA: Verilog: ternary patch
From: Stephen Williams <steve@icarus.com>
Date: Thu, 09 Sep 1999 09:22:00 -0700
Delivery-Date: Thu Sep 9 12:22:20 1999
Delivery-Date: Thu, 09 Sep 1999 12:24:12 -0400
In-Reply-To: Your message of "Thu, 09 Sep 1999 04:09:13 PDT." <199909091109.EAA13451@halibut.imedia.com>
Reply-To: geda-dev@seul.org
Sender: owner-geda-dev@seul.org


pmonta@halibut.imedia.com said:
> I got tired of replacing ternary expressions with if statements---here
> is an elaborator.


Structural (net) elaboration, yes I see. This will do for now, but
eventually it will be replaced with a LPM MUX device. However, the
feature freeze leads me to accept your patch instead.

Also, thanks for the other operators. I'll take a closer look at
(and probably apply) the whole patch this afternoon.
-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."

Follow-Ups:
- Re: gEDA: Verilog: ternary patch
  - From: Peter Monta <pmonta@halibut.imedia.com>

References:
- gEDA: Verilog: ternary patch
  - From: Peter Monta <pmonta@halibut.imedia.com>

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