Re: gEDA: Verilog: ternary test code

To: geda-dev@geda.seul.org
Subject: Re: gEDA: Verilog: ternary test code
From: Peter Monta <pmonta@halibut.imedia.com>
Date: Thu, 9 Sep 1999 11:18:18 -0700
Delivery-Date: Thu Sep 9 14:18:44 1999
Delivery-Date: Thu, 09 Sep 1999 14:20:37 -0400
In-reply-to: <99090922264401.11822@newsys.frmt1.sfba.home.com> (message fromSteve Wilson on Thu, 9 Sep 1999 22:24:13 -0700)
References: <199909091118.EAA13487@halibut.imedia.com> <99090922264401.11822@newsys.frmt1.sfba.home.com>
Reply-To: geda-dev@seul.org
Sender: owner-geda-dev@seul.org

> bvec = 4'bzx10 ;

Ah, of course, obvious once you see it; thanks.

Cheers,
Peter Monta   pmonta@imedia.com
Imedia Corp.

References:
- gEDA: Verilog: ternary test code
  - From: Peter Monta <pmonta@halibut.imedia.com>
- Re: gEDA: Verilog: ternary test code
  - From: Steve Wilson <stevew@home.com>