gEDA: Hardware accelerated simulation

[Stephen Williams <steve@icarus.com>]

I've mentioned before in this forum the idea of designing a hardware
accelerator for simulations and writing a back-end to ivl that targets
that hardware.

It turns out someone else thinks that's a practical idea. If you have
access to the August 23 EE-Times, find the article:

	"SoC verification demands FPGA speeds"

on page 86. There are actually a few decent ideas in amongst all that
marketing drivel:-)

Anybody interested in writing some verilog code to implement a discrete
event simulation machine?-)

-- 
Steve Williams                "The woods are lovely, dark and deep.
steve@icarus.com              But I have promises to keep,
steve@picturel.com            and lines to code before I sleep,
http://www.picturel.com       And lines to code before I sleep."