Re: gEDA: Hardware accelerated simulation

[Roger Dingledine <arma@mit.edu>]

> > "SoC verification demands FPGA speeds"
> > ...
> > Anybody interested in writing some verilog code to implement a discrete
> > event simulation machine?-)
> 
> Ah, but how to verify it?  :-) :-)
> 
> I don't know if the EE Times article you mention refers
> to the same product, but Synplicity announced a tool
> aimed at this market recently, called Certify:
> 
> http://www.synplicity.com/products/Certify.html
> 
> I'm wondering how practical it might be to run simulations on
> general-purpose clusters, similar to the Beowulf effort for scientific
> computation.  One can imagine using some partitioning scheme to try to
> mitigate the high intermachine latency; in the extreme case of a fully
> synchronous design, each machine would say to the others "here is what
> happened to my state on this clock".
 
Not that I know much about what you're talking about from a EE perspective,
but I bet if it was a worthy cause ("I'm doing hardware designs that I'm
going to give out as 'free' when I'm done" counts), and if you had a large
number of jobs (because the latency really would be high, so you'd want one
job per machine), you could do a net-wide effort where people donate cycles
to your job. Certainly there would be a couple of dozen machines that could
do computation for the gEDA project if such computation were needed; with a
bit of publicity, it could turn into a couple hundred or even more.

I implemented a 24*PIII/550 Beowulf over the summer; consequently, I have
the socket-level clue to make this happen in a number of different ways, if
you can provide the justification. :)

It sounds like a given job is very large, so some mechanism for breaking
it into pieces would be necessary. But a public pool of cpu's to draw from
would be much more useful long-term than a Beowulf that belongs to only one
organization/company.

--Roger