Re: gEDA-user: Dead Copper

["J.D. Bakker" <jdb@xxxxxxxxxxxx>]

> - Last, and clearly the most important, in this layout, the isolated 
> rectangle of copper at the lower right is still considered to be 
> electrically connected to the rest of the copper polygon.  In other 
> words this represents a situation where the tool might tell you that 
> you  have connected up everything but you might not have in reality.

Automated detection of islands is non-trivial. Detection of 
*unconnected* islands is harder still. Imagine a multilayer board 
with ground planes on several layers, and vias interconnecting the 
planes. I know of no simple algorithm to determine the connectivity 
of such a setup.

Several years ago I wrote a connection checker / copper removal tool 
for an in-house PCB tool, with sliver removal as one of the goals 
(source long gone, alas). IIRC I ended up rendering all layers to 
bitmaps with 1 mil resolution, and did a flood fill to find 
unconnected areas. I think I used the solder mask as a heuristic to 
tell SMD pads from dead copper. Processing a 3x4in 6-layer board 
would take about an hour, on a Pentium Pro/200 (but I believe the 
program was memory bound, not CPU bound). Still, you'd want to use 
this as a final check before sending a board to be fabbed, not as a 
real time DRC.

A tool like this is full of special cases. Without assistance the 
software can't tell heatsink areas, patch antenna resonators or 
microwave filters from dead copper.

JD 'Mr. Positivity' B.
--
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