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gEDA-user: Hierarchical Verilog design with BUS

Hi All,

Attached is a package which contains a Hierarchy
source report script. It can generate Hierarchical
Verilog netlist, and also other forms of hierarchy
report which may help in your design.

An example is also included to demonstrate how
do do Hierarchical Verilog design with BUS.

Best Regards,
Paul Tan

Attachment: geda_hier_tools.tar.gz
Description: application/gzip-compressed


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