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Re: gEDA-user: High speed decoupling (was: Simulation of ceramic capacitors, pairs and groups)




On Mar 7, 2006, at 6:53 PM, Evan Lavelle wrote:

Karel Kulhavy wrote:
I have made a simulation to see how the capacitor pairs and groups actually
behave:
http://ronja.twibright.com/technotes/cercap.php

Thanks; very nice. However, I'm not sure that the numbers are right. The figure shows that a 10nF//100nF pair gives a low impedance (< ~1 Ohm) over a range of about 1.5MHz to 200MHz, which would make it ideal for decoupling high speed parts. I compared this with an old Cypress HOTLink app note where 22nF//100nF pairs were analysed, and the author's opinion was that this wasn't suitable for high-speed decoupling, because of a high resonant peak (~ 100 Ohm) at 150MHz. Your results show a peak of about 0.4 Ohm (at 30MHz), so are much better.


The differences are:

1) The appnote assumes real parasitics of 5nH for a surface-mounted MLC cap, compared to your manufacturer's figures of 1.6 - 1.9nH. Your figures also seem to be for leaded caps: the SM figures are even lower.

2) The appnote gives a lower ESR of about 30 mOhm, while you're using 100 - 150 mOhm. The peak height varies inversely with the ESR.

Anyone have any other thoughts on real in-system ESL and ESR numbers?

An inductor is a concentration of magnetic energy. A wirewound resistor also concentrates magnetic energy to some extent. For these it's sensible to associate an inductance. But common capacitor construction doesn't concentrate magnetic energy. If current flows there will be magnetic energy present, but little of it will be inside the capacitor: it will be in the neighborhood, but the capacitor doesn't control its energy or configuration by itself. So, if you want to model the inductance associated with that magnetic energy where should it go in the circuit? This is why to really do these problems right you need an electromagnetic field solver, although a multimode transmission line model is often adequate. For estimates, start by thinking 1nH/mm.


ESL specs from capacitor manufacturers tell you more about their test fixtures than they do about capacitors, but many engineers don't know enough physics to realize this. Of course, the test fixture is often similar to a real circuit so it isn't completely silly, but it's really more important to understand how to estimate inductance from geometry, especially in EMI problems where stray *mutual* inductance can be a big deal (and no data sheet can tell you that).

ESR is more relevant, but in real circuits with ceramic capacitors resistance due to skin effect on the PCB traces is usually more important, especially when considering Q of parasitic resonances.

John Doty              Noqsi Aerospace, Ltd.
jpd@xxxxxxxxxxxxx