Re: gEDA-user: generate within verilog

[ldoolitt@xxxxxxxxxxxxxxx]

SImon -

On Thu, Mar 08, 2007 at 06:07:54AM +0000, ST de Feber wrote:
> Are you sure it is icarus or the construct itself ?
> Have you tried it with e.q modelsim ?

Well, that's what I hoped someone else on the list could
tell me.  I don't have access to or experience with modelsim.

Steve Williams beat everyone to to the punch, though.
He just posted a fix to Icarus, it now runs that code just fine.
Thanks, Steve!

It's easy to assume it will run on most other Verilog simulators, too.
It also synthesizes without error on Xilinx XST, but I haven't confirmed
functionality on the chip.

   - Larry


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