gEDA-user: What's your way of syncing CPLD design and gschem symbols???

[Christoph LECHNER <cl0023@xxxxxxx>]

Hi!

How do you keep your Xilinx CPLD design in sync w/
your gschem symbol files?

I mean, after you have drawn all your schematics and
build up the essentials of your CPLD design (esp. the
pins must exist :)), when doing the PCB artwork shuffling
the CPLD pins can give a really improved PCB layout ...

But the problem for me was to keep the symbol in sync
w/ the Xilinx Fitter report, so to do the work auto-
matically I hacked a Perl script (~6kB) last year,
but before adding some required upgrades & improvements
to the script I just wanted to ask how you do the sync
job!

For those not familiar with the Xilinx report files
I added a example Xilinx pin-out report for a small
Xilinx device (sorry for the attachment!)
Files with this structure are converted to symbols.

BTW: How do split up large ICs in multiple (different)
symbols? For example: One symbol for power, clk and JTAG
and one symbol for the rest of the design. I would create
the symbols and give them the same refdes ... don't know
if this is the correct way to make it work!

- cl

Pin List

Pin Num	Pin Type	Assigned Signal
1	I/O	clko1
2	I/O	rst
3	I/O	rotenc_b
4	I/O	hid_irq
5	I/O/GCK1	clki1
6	I/O/GCK2	clki2
7	I/O/GCK3	pclk
8	I/O	PGND
9	I/O	PGND
10	GND	GND
11	I/O	q_in<0>
12	I/O	q_in<1>
13	I/O	PGND
14	I/O	tp<5>
15	TDI	TDI
16	TMS	TMS
17	TCK	TCK
18	I/O	tp<4>
19	I/O	tp<3>
20	I/O	tp<2>
21	VCCINT	VCC
22	I/O	tp<6>
23	GND	GND
24	I/O	rotenc_pb
25	I/O	rotenc_a
26	I/O	lcd_cp
27	I/O	tp<7>
28	I/O	pb_b
29	I/O	tp<1>
30	TDO	TDO
31	GND	GND
32	VCCIO	VCC
33	I/O	q_in<2>
34	I/O	tp<0>
35	I/O	clko2
36	I/O	pb_c
37	I/O	lcd_sd
38	I/O	l_q_in
39	I/O/GSR	sclk
40	I/O/GTS2	pb_a
41	VCCINT	VCC
42	I/O/GTS1	pb_d
43	I/O	queue_irq
44	I/O	q_in<3>

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