Re: gEDA-user: OT: Opencores CORDIC - bugs?

[Magnus Danielson <cfmd@xxxxxxxxxxxx>]

From: Peter Clifton <pcjc2@xxxxxxxxx>
Subject: gEDA-user: OT: Opencores CORDIC - bugs?
Date: Sat, 10 Mar 2007 04:14:19 +0000
Message-ID: <1173500059.5759.15.camel@localhost>

> Hi,

Peter,

> I was just curios if anyone on list has used the open-cores cordic VHDL.

Haven't played with that. Haven't had the need so far.

> I'm using it to generate a reference waveform for a PWM generator, and
> have been bashing my head against the wall with little oddities and
> glitches like different results for +ve and -ve angles (which should
> read the same for cosine).
> 
> Eventually, I tracked it down to the HDL which divides by a power of two
> in the cordic pipeline. Put simply... it doesn't work for -ve numbers.
> 
> In twos complement - for the specific implementation used at least -
> which sign extends with the original MSB:
> 
> 	-2 >> 1 == -1
> 	-1 >> 1 == -1
> 	      (etc..)
> 
> Clearly this is different from the behaviour for +ve numbers, hence he
> discrepency I noted.
> 
> Does anyone per chance know an efficient hardware algorithm which can
> produce the same /2 results for +ve and -ve twos complement numbers?

Shift left with sign extention?

half(30 downto 0) <= whole(31 downto 1);
half(31)          <= whole(31);

Should do it. Very efficient.

If you try it on -2 you expect -1:
1111 1111 1111 1111 1111 1111 1111 1110
=>
1111 1111 1111 1111 1111 1111 1111 1111

If you try it on 2 you expect 1:
0000 0000 0000 0000 0000 0000 0000 0010
=>
0000 0000 0000 0000 0000 0000 0000 0001

-3 will become -1 just as 3 will become 1. Thus, it is symmetric around 0.
This _may_ not be what you are after. You might require rounding such that
-1 / 2 become 0. This is kind of running into the IEEE-754 field, but with
whole numbers. Regardless of which you need, it should be obvious how to
extend this. An adder-chain for the rounding is a good hint I think, but only
if you really need it.

> Depending on which stage in the cordic pipeline, the shift may be up to
> one less than a whole word length. I've no idea how this ends up being
> synthesised in an FPGA.

I would have to take a look in the CORDIC code, but I don't have the time now.

> My current work around is to test for negativity, take the -ve if it is
> -ve, (giving a +ve), do the shift, then take the -ve again (if the
> original was -ve).
> 
> Perhaps the best way is for me to keep the cordic operating in the
> 0<->45 degree angle range, rather than the -45<->45 I've been using so
> far.
> 
> Any thoughts?

Cheers,
Magnus


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