Re: gEDA-user: GEDA: Polygon integrity check

[Ben Jackson <ben@xxxxxxx>]

On Mon, Sep 01, 2008 at 11:46:05AM -0700, Dave N6NZ wrote:
> So I've just completed a (2 layer) board where it was a challenge to 
> keep the ground and power planes from getting chewed up beyond 
> usefulness.

Yes, I did something similar and filed a bug as a result.

PCB should eliminate slivers of planes that are thinner than the min
trace width, and then use that to understand the connectivity.
Unfortunately that doesn't fit well with the polygon system as it
stands.  A DRC to warn is more likely, but there are still no tools
to fix that manually.  If the DRC said "this sliver is too narrow" it
still wouldn't readily apply to finding (lack of) connectivity.

> about thin necks in polygons.  How hard would it be to do a computation 
> like that?

Using the existing polygon mechanism it might be possible to take the
copper plane outline (post-clearance) and turn it into a new polygon
that's an outline of the min trace width.  Anywhere the outline touches
itself could be a problem.  I'm not sure it *must* be a problem though.

-- 
Ben Jackson AD7GD
<ben@xxxxxxx>
http://www.ben.com/


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