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Re: Speeding up slow/missed things... Re: [f-cpu] Supported Instructions



hi,

Andreas Romeyke wrote:
> Hello,
> On Sat, 6 Apr 2002, Yann Guidon wrote:
> > way to perform the task. If you want to speed it up too much, you
> > will make the architecture and programming model too complex and
> > not implementable. And don't forget your P&H books :-) (you know,
> > "what is the definition of RISC"...)
> 
> In my mind there bubbles the idea of protected Cacheareas. If we have a
> special opcode to lock/unlock  a range on the cache with emulation
> code... ...than it is possible that an OS use it for a fast
> software-emulation of FP or somewhat...

and TLB misses.

> Another advantage is that we transform the coding-hardware-process into
> coding-software. Coding software can do a wider range of developers as
> conding hardware like VHDL and so.
> 
> Is this a possible way to do this? Any hints?

Cache locking was an issue some time ago and is often used in real-time
chips (ie TI DSPs). However, there is still the problem of allowing
users to use it (protection issue which is not found in DSPs and
embedded CPUs). But this is certainly a desirable issue, at least for
the L2 cache (if it's used often, it will be cached in L1 too).

There is an old entry about this in the F-CPU manual, but there is
no agreement for the interface (some misunderstandings.)

> Bye Art1
WHYGEE
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