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Rep:Re: [f-cpu] RC5, F-CPU and srotl

> > I think that it will do :
> > for i := imm6(1) to imm6(1) + imm6(2) do
> >   store 8, ri, [r3]
> > done
> > or some think like that.
> no, because
>  - please don't add an adder in the Critical DataPath
The add operation is needed, and we must check if he can do is save
starting the storem/loadm, I see the problem, and the difference with
srb mechanism.

>>> I forget to speak about that in my later email. Firstly, i had
argred with Whygee to remove all adder in the critical data path to
reduice at the minimum this cdp. So the latency for common instructions
will be reduice.
BUT without such adder in "many" case it signify adding a new
instruction to do the jobs. So it's increase the code size (i have
understood that it's the main fear of Christophe about Fcpu ISA). But it
add a RAW dependancies, too, the worst one. And it increase the register
pressure (because a temporary register is needed).
From an other point of view, we could see that we reduice the average
cpi of the fcpu compare to other cpu. That's not really the good way to
add mips to our core.
The question is to quantify how many times we will see such construct in
typical code compare to the gain of 1 pipeline stage.


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