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Re: [f-cpu] RC5, F-CPU and srotl

hi !

cedric wrote:
> What I want to do by the port of the dnetc client is to see where we can have
> problem with our instruction set on high parellisable algorithm. The
> conclusion of this discussion is that we will have a "real" simd rotl, but
> not because of this algorithm, but because we want a "clean" CPU.

you can write that in the README for your example :-)

> > What's a 64-bit CPU good for, compared to a 32-bit one? It's not
> > necessarily faster, but it can handle large working sets. Therefore
> > I'd rather focus on scientific applications, databases and so on.
> Yes, but we need to start from a point, if you have some idee of which
> algorithm or part of program to port, say it here, and if some one have time
> he can start to port them.
i had a first version of a 8-tap Winograd FFT that was optimised for FC0.
The code is more or less ready but i wanted to add more stuff like
demonstration code and a verification program (to check whether there was
no error done during the algorithm's modification).

> > > The case of dnet is looking different but i can't involve myself
> > > in this now. The case of the SIMD shift has been proved and there
> > > does not seem to be any difficulty in implementing it with F-CPU,
> > > we simply disagree on a "small" implementation detail :-)
> > Huh? No difficulty?
> I see your last post, so you find a solution, no ? ;-)

didn't i show you what i wanted to do ?
 - 1 SDUP stage (to propagate the control signals and/or perform sdup)
 - 1 shift-16 stage (made of mux-4)
 - 3 levels of shift-16 (made of mux-3)
=> we can split the pipeline after the first shift-16

I can't develop now because i'm deep into LFS problems.
i wish to solve all my OS problems for good in the near future
so i'll be back at VHDL programming before my own brain coredumps...

> A+
>    Cedric
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