[f-cpu] Re: Navier-Stokes

[Yann Guidon <whygee@f-cpu.org>]

hello,

Juergen Goeritz wrote:
> Ji YG,
> 
> are you also thinking about several caching strategies
> for f-cpu? I can think of LRU data cache as not being
> always the best strategy when computing big arrays, e.g.
> big array mult. What's your opinion, could there also be
> a PCL (partially cache lock) or a ULA (update last again)
> or a UR (update randomly) strategy?

i don't know why you called this cache-related post "Navier-Stokes",
unless you have an idea ;-)

FC0 controls the L1 cache and uses 2 means to control the data locality :
 - L1 works with LRU or whatever strategy the user implements.
   Personally i have better confidence in LRU because it's more
   predictive than others.
 - cache hinting flags : the load/store instructions have a flag
   that indicates whether the accessed line can be stored in L1
   or directly flushed outside of FC0. So if you know that you won't
   reuse this data, this bypasses the L1 "buffer" (because it acts
   as a huge FIFO for the write back).

Together and with some adaptative algorithms, this is enough AFAIK.
Adaptative strip-mining is an efficient way to process large data sets
at the speed of the L1. I think that multi-level strip-mining is also
possible, though a bit more complex, but if i think what you think correctly,
this will do the trick.

readU,
> JG
WHYGEE
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